Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	412	1			T18	14		T29	4		T166	4
all_values[1]	412	1			T18	14		T29	4		T166	4
all_values[2]	412	1			T18	14		T29	4		T166	4
all_values[3]	412	1			T18	14		T29	4		T166	4
all_values[4]	412	1			T18	14		T29	4		T166	4
all_values[5]	412	1			T18	14		T29	4		T166	4
all_values[6]	412	1			T18	14		T29	4		T166	4
all_values[7]	412	1			T18	14		T29	4		T166	4
all_values[8]	412	1			T18	14		T29	4		T166	4
all_values[9]	412	1			T18	14		T29	4		T166	4
all_values[10]	412	1			T18	14		T29	4		T166	4
all_values[11]	412	1			T18	14		T29	4		T166	4
all_values[12]	412	1			T18	14		T29	4		T166	4
all_values[13]	412	1			T18	14		T29	4		T166	4
all_values[14]	412	1			T18	14		T29	4		T166	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3408

1

T18

94

T29

39

T166

33

auto[1]

2772

1

T18

116

T29

21

T166

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T18

8

T29

11

T166

18

auto[1]

5158

1

T18

202

T29

49

T166

42

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3649

1

T18

110

T29

36

T166

37

auto[1]

2531

1

T18

100

T29

24

T166

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	52	1			T29	1		T101	4		T269	5
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T18	3		T29	2		T166	3
all_values[0]	auto[0]	auto[1]	auto[0]	25	1			T227	1		T270	4		T271	2
all_values[0]	auto[0]	auto[1]	auto[1]	91	1			T18	5		T227	1		T268	4
all_values[0]	auto[1]	auto[0]	auto[1]	84	1			T18	1		T268	3		T269	1
all_values[0]	auto[1]	auto[1]	auto[1]	86	1			T18	5		T29	1		T166	1
all_values[1]	auto[0]	auto[0]	auto[0]	55	1			T29	1		T166	3		T269	1
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T18	7		T29	1		T227	1
all_values[1]	auto[0]	auto[1]	auto[0]	27	1			T18	1		T29	1		T166	1
all_values[1]	auto[0]	auto[1]	auto[1]	84	1			T18	2		T227	2		T268	3
all_values[1]	auto[1]	auto[0]	auto[1]	92	1			T18	4		T29	1		T101	1
all_values[1]	auto[1]	auto[1]	auto[1]	68	1			T227	1		T268	1		T269	3
all_values[2]	auto[0]	auto[0]	auto[0]	52	1			T18	1		T166	3		T272	1
all_values[2]	auto[0]	auto[0]	auto[1]	97	1			T18	2		T227	1		T268	3
all_values[2]	auto[0]	auto[1]	auto[0]	24	1			T166	1		T227	2		T273	1
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T18	4		T29	3		T101	3
all_values[2]	auto[1]	auto[0]	auto[1]	84	1			T18	2		T29	1		T101	1
all_values[2]	auto[1]	auto[1]	auto[1]	74	1			T18	5		T227	1		T268	3
all_values[3]	auto[0]	auto[0]	auto[0]	56	1			T18	1		T29	1		T268	1
all_values[3]	auto[0]	auto[0]	auto[1]	101	1			T18	2		T29	2		T166	1
all_values[3]	auto[0]	auto[1]	auto[0]	25	1			T18	1		T272	2		T274	1
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T18	2		T166	1		T268	2
all_values[3]	auto[1]	auto[0]	auto[1]	91	1			T18	3		T227	1		T101	1
all_values[3]	auto[1]	auto[1]	auto[1]	67	1			T18	5		T29	1		T166	2
all_values[4]	auto[0]	auto[0]	auto[0]	37	1			T166	1		T227	2		T269	1
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T18	4		T29	1		T227	1
all_values[4]	auto[0]	auto[1]	auto[0]	33	1			T18	1		T166	3		T269	1
all_values[4]	auto[0]	auto[1]	auto[1]	88	1			T18	4		T268	4		T269	7
all_values[4]	auto[1]	auto[0]	auto[1]	95	1			T18	1		T29	3		T101	3
all_values[4]	auto[1]	auto[1]	auto[1]	82	1			T18	4		T227	1		T269	2
all_values[5]	auto[0]	auto[0]	auto[0]	40	1			T29	1		T101	1		T269	2
all_values[5]	auto[0]	auto[0]	auto[1]	93	1			T18	2		T29	2		T166	2
all_values[5]	auto[0]	auto[1]	auto[0]	25	1			T227	2		T101	3		T269	1
all_values[5]	auto[0]	auto[1]	auto[1]	88	1			T18	4		T268	4		T269	5
all_values[5]	auto[1]	auto[0]	auto[1]	99	1			T18	3		T166	1		T227	1
all_values[5]	auto[1]	auto[1]	auto[1]	67	1			T18	5		T29	1		T166	1
all_values[6]	auto[0]	auto[0]	auto[0]	40	1			T227	1		T269	2		T273	1
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T18	2		T166	1		T227	1
all_values[6]	auto[0]	auto[1]	auto[0]	32	1			T166	1		T269	2		T273	1
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T18	6		T29	2		T227	1
all_values[6]	auto[1]	auto[0]	auto[1]	107	1			T18	4		T29	2		T166	2
all_values[6]	auto[1]	auto[1]	auto[1]	76	1			T18	2		T268	3		T269	4
all_values[7]	auto[0]	auto[0]	auto[0]	42	1			T227	2		T268	3		T114	1
all_values[7]	auto[0]	auto[0]	auto[1]	86	1			T18	1		T29	1		T227	1
all_values[7]	auto[0]	auto[1]	auto[0]	30	1			T113	1		T270	1		T271	1
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T18	5		T29	1		T166	1
all_values[7]	auto[1]	auto[0]	auto[1]	91	1			T18	4		T29	1		T166	1
all_values[7]	auto[1]	auto[1]	auto[1]	77	1			T18	4		T29	1		T166	2
all_values[8]	auto[0]	auto[0]	auto[0]	50	1			T29	1		T272	1		T275	1
all_values[8]	auto[0]	auto[0]	auto[1]	96	1			T18	4		T166	3		T227	1
all_values[8]	auto[0]	auto[1]	auto[0]	16	1			T276	1		T277	2		T278	1
all_values[8]	auto[0]	auto[1]	auto[1]	76	1			T18	4		T29	1		T227	1
all_values[8]	auto[1]	auto[0]	auto[1]	107	1			T18	2		T101	2		T268	1
all_values[8]	auto[1]	auto[1]	auto[1]	67	1			T18	4		T29	2		T166	1
all_values[9]	auto[0]	auto[0]	auto[0]	40	1			T18	1		T227	1		T101	1
all_values[9]	auto[0]	auto[0]	auto[1]	111	1			T18	1		T29	2		T166	2
all_values[9]	auto[0]	auto[1]	auto[0]	26	1			T18	2		T101	1		T276	2
all_values[9]	auto[0]	auto[1]	auto[1]	70	1			T18	1		T29	1		T268	4
all_values[9]	auto[1]	auto[0]	auto[1]	96	1			T18	5		T29	1		T166	1
all_values[9]	auto[1]	auto[1]	auto[1]	69	1			T18	4		T166	1		T268	3
all_values[10]	auto[0]	auto[0]	auto[0]	34	1			T269	1		T272	7		T114	2
all_values[10]	auto[0]	auto[0]	auto[1]	96	1			T18	2		T29	2		T166	1
all_values[10]	auto[0]	auto[1]	auto[0]	16	1			T269	1		T114	1		T279	2
all_values[10]	auto[0]	auto[1]	auto[1]	94	1			T18	5		T227	2		T101	1
all_values[10]	auto[1]	auto[0]	auto[1]	94	1			T18	5		T29	2		T166	1
all_values[10]	auto[1]	auto[1]	auto[1]	78	1			T18	2		T166	2		T268	5
all_values[11]	auto[0]	auto[0]	auto[0]	37	1			T29	4		T101	1		T280	1
all_values[11]	auto[0]	auto[0]	auto[1]	87	1			T18	2		T166	2		T101	1
all_values[11]	auto[0]	auto[1]	auto[0]	25	1			T280	1		T281	1		T115	2
all_values[11]	auto[0]	auto[1]	auto[1]	95	1			T18	3		T227	1		T268	3
all_values[11]	auto[1]	auto[0]	auto[1]	93	1			T18	5		T101	2		T268	4
all_values[11]	auto[1]	auto[1]	auto[1]	75	1			T18	4		T166	2		T227	3
all_values[12]	auto[0]	auto[0]	auto[0]	33	1			T166	2		T101	2		T268	1
all_values[12]	auto[0]	auto[0]	auto[1]	100	1			T18	4		T29	1		T227	1
all_values[12]	auto[0]	auto[1]	auto[0]	25	1			T166	2		T113	1		T114	3
all_values[12]	auto[0]	auto[1]	auto[1]	88	1			T18	3		T227	1		T101	1
all_values[12]	auto[1]	auto[0]	auto[1]	86	1			T18	1		T29	2		T227	2
all_values[12]	auto[1]	auto[1]	auto[1]	80	1			T18	6		T29	1		T101	1
all_values[13]	auto[0]	auto[0]	auto[0]	33	1			T101	1		T268	3		T270	1
all_values[13]	auto[0]	auto[0]	auto[1]	75	1			T18	3		T166	1		T227	1
all_values[13]	auto[0]	auto[1]	auto[0]	27	1			T166	1		T101	3		T113	2
all_values[13]	auto[0]	auto[1]	auto[1]	102	1			T18	6		T29	1		T227	1
all_values[13]	auto[1]	auto[0]	auto[1]	109	1			T18	1		T29	2		T166	1
all_values[13]	auto[1]	auto[1]	auto[1]	66	1			T18	4		T29	1		T166	1
all_values[14]	auto[0]	auto[0]	auto[0]	37	1			T29	1		T227	1		T101	1
all_values[14]	auto[0]	auto[0]	auto[1]	97	1			T18	8		T227	1		T268	6
all_values[14]	auto[0]	auto[1]	auto[0]	28	1			T101	3		T275	1		T113	2
all_values[14]	auto[0]	auto[1]	auto[1]	79	1			T18	1		T29	2		T166	1
all_values[14]	auto[1]	auto[0]	auto[1]	93	1			T18	3		T166	1		T227	1
all_values[14]	auto[1]	auto[1]	auto[1]	78	1			T18	2		T29	1		T166	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal