Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31204289	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7641957

1

T1

34

T2

26

T3

104

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38042735	1			T1	74		T2	27		T3	351
values[0x0]	400509	1			T1	34		T2	36		T3	72
values[0x1]	403002	1			T1	44		T2	25		T3	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21758999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17087247

1

T1

58

T2

41

T3

216

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	171087	1			T1	1		T5	91		T7	235
valid_sources[0x01]	148631	1			T1	1		T5	47		T7	245
valid_sources[0x02]	143550	1			T5	125		T7	274		T8	57
valid_sources[0x03]	149837	1			T1	1		T2	7		T5	79
valid_sources[0x04]	142102	1			T5	91		T7	297		T8	83
valid_sources[0x05]	136619	1			T5	80		T7	258		T8	73
valid_sources[0x06]	163089	1			T1	2		T5	64		T7	259
valid_sources[0x07]	147314	1			T5	96		T7	305		T8	70
valid_sources[0x08]	140776	1			T1	5		T5	73		T7	247
valid_sources[0x09]	148355	1			T5	83		T7	258		T8	63
valid_sources[0x0a]	153849	1			T1	1		T5	105		T7	268
valid_sources[0x0b]	155873	1			T5	79		T7	296		T8	81
valid_sources[0x0c]	158321	1			T5	58		T7	216		T8	81
valid_sources[0x0d]	155609	1			T1	1		T5	90		T7	225
valid_sources[0x0e]	142825	1			T5	65		T7	279		T8	76
valid_sources[0x0f]	162065	1			T1	1		T5	82		T7	236
valid_sources[0x10]	176145	1			T3	4		T5	83		T7	229
valid_sources[0x11]	147921	1			T1	1		T5	72		T7	232
valid_sources[0x12]	154100	1			T1	1		T5	107		T7	226
valid_sources[0x13]	146560	1			T1	2		T5	58		T7	233
valid_sources[0x14]	140790	1			T1	4		T5	83		T7	224
valid_sources[0x15]	163484	1			T5	53		T7	268		T8	80
valid_sources[0x16]	145534	1			T5	83		T7	221		T8	90
valid_sources[0x17]	158374	1			T5	72		T7	246		T8	103
valid_sources[0x18]	146480	1			T1	1		T5	68		T7	268
valid_sources[0x19]	138606	1			T5	94		T7	226		T8	76
valid_sources[0x1a]	144510	1			T5	130		T7	221		T8	80
valid_sources[0x1b]	145998	1			T5	58		T7	234		T8	62
valid_sources[0x1c]	146429	1			T1	2		T5	98		T7	243
valid_sources[0x1d]	161674	1			T5	95		T7	230		T8	88
valid_sources[0x1e]	300079	1			T5	86		T7	259		T8	71
valid_sources[0x1f]	135307	1			T5	77		T7	238		T8	61
valid_sources[0x20]	140394	1			T1	2		T5	64		T7	258
valid_sources[0x21]	148070	1			T5	45		T7	252		T8	87
valid_sources[0x22]	142037	1			T5	72		T7	282		T8	80
valid_sources[0x23]	130596	1			T1	1		T5	70		T7	257
valid_sources[0x24]	149821	1			T5	65		T7	207		T8	72
valid_sources[0x25]	148823	1			T5	86		T7	280		T8	78
valid_sources[0x26]	150221	1			T2	1		T5	74		T7	235
valid_sources[0x27]	139110	1			T5	106		T7	224		T8	58
valid_sources[0x28]	143589	1			T5	106		T7	258		T8	78
valid_sources[0x29]	140108	1			T1	1		T5	66		T7	251
valid_sources[0x2a]	135381	1			T2	1		T5	102		T7	221
valid_sources[0x2b]	136599	1			T5	67		T7	246		T8	70
valid_sources[0x2c]	130779	1			T1	2		T5	126		T7	256
valid_sources[0x2d]	157270	1			T1	2		T5	71		T7	212
valid_sources[0x2e]	157077	1			T1	1		T5	55		T7	251
valid_sources[0x2f]	144951	1			T5	78		T7	250		T8	72
valid_sources[0x30]	145704	1			T1	4		T5	77		T7	255
valid_sources[0x31]	150673	1			T5	70		T7	234		T8	55
valid_sources[0x32]	149854	1			T1	1		T5	56		T7	278
valid_sources[0x33]	149690	1			T5	52		T7	241		T8	84
valid_sources[0x34]	155519	1			T5	80		T7	238		T8	82
valid_sources[0x35]	158789	1			T1	4		T5	93		T7	221
valid_sources[0x36]	142768	1			T5	72		T7	238		T8	82
valid_sources[0x37]	140284	1			T1	4		T5	100		T7	255
valid_sources[0x38]	132681	1			T5	77		T7	263		T8	69
valid_sources[0x39]	155684	1			T1	1		T5	98		T7	249
valid_sources[0x3a]	162132	1			T5	95		T7	288		T8	84
valid_sources[0x3b]	143299	1			T1	1		T5	62		T7	290
valid_sources[0x3c]	139290	1			T5	118		T7	261		T8	73
valid_sources[0x3d]	152793	1			T1	1		T5	56		T7	268
valid_sources[0x3e]	138365	1			T1	2		T5	59		T7	259
valid_sources[0x3f]	142256	1			T5	84		T7	223		T8	68
valid_sources[0x40]	143027	1			T1	2		T5	58		T7	288
valid_sources[0x41]	144928	1			T5	94		T7	218		T8	67
valid_sources[0x42]	151556	1			T5	77		T7	270		T8	77
valid_sources[0x43]	165886	1			T5	62		T7	289		T8	86
valid_sources[0x44]	132812	1			T1	2		T5	102		T7	273
valid_sources[0x45]	143622	1			T5	78		T7	207		T8	78
valid_sources[0x46]	149687	1			T5	94		T7	178		T8	81
valid_sources[0x47]	201668	1			T1	4		T5	78		T7	260
valid_sources[0x48]	126615	1			T5	64		T7	258		T8	80
valid_sources[0x49]	180125	1			T5	73		T7	219		T8	72
valid_sources[0x4a]	158141	1			T5	46		T7	287		T8	79
valid_sources[0x4b]	133234	1			T5	72		T7	262		T8	82
valid_sources[0x4c]	146665	1			T5	59		T7	214		T8	82
valid_sources[0x4d]	150131	1			T1	2		T5	70		T7	236
valid_sources[0x4e]	168902	1			T5	79		T7	258		T8	91
valid_sources[0x4f]	154118	1			T1	3		T5	78		T7	241
valid_sources[0x50]	147419	1			T1	1		T5	101		T7	270
valid_sources[0x51]	136030	1			T5	99		T7	232		T8	70
valid_sources[0x52]	147056	1			T5	52		T7	227		T8	69
valid_sources[0x53]	165471	1			T5	113		T7	278		T8	75
valid_sources[0x54]	162213	1			T5	68		T7	223		T8	74
valid_sources[0x55]	150804	1			T5	83		T7	223		T8	79
valid_sources[0x56]	149942	1			T5	85		T7	228		T8	77
valid_sources[0x57]	131529	1			T5	87		T7	290		T8	73
valid_sources[0x58]	161704	1			T5	80		T7	246		T8	77
valid_sources[0x59]	139902	1			T5	114		T7	279		T8	65
valid_sources[0x5a]	149187	1			T5	73		T7	230		T8	88
valid_sources[0x5b]	144651	1			T1	3		T5	99		T7	258
valid_sources[0x5c]	152357	1			T1	1		T5	63		T7	245
valid_sources[0x5d]	143678	1			T5	84		T7	269		T8	84
valid_sources[0x5e]	147737	1			T2	10		T5	79		T7	224
valid_sources[0x5f]	161496	1			T5	108		T7	279		T8	71
valid_sources[0x60]	145908	1			T1	3		T5	75		T7	230
valid_sources[0x61]	158121	1			T5	90		T7	251		T8	96
valid_sources[0x62]	148056	1			T5	71		T7	277		T8	75
valid_sources[0x63]	138710	1			T5	104		T7	282		T8	82
valid_sources[0x64]	155196	1			T5	63		T7	279		T8	67
valid_sources[0x65]	137930	1			T1	2		T5	99		T7	263
valid_sources[0x66]	142800	1			T5	69		T7	313		T8	83
valid_sources[0x67]	159153	1			T5	82		T7	221		T8	72
valid_sources[0x68]	148603	1			T5	80		T7	217		T8	80
valid_sources[0x69]	145347	1			T1	3		T5	73		T7	262
valid_sources[0x6a]	153001	1			T5	75		T7	244		T8	61
valid_sources[0x6b]	155114	1			T5	77		T7	256		T8	82
valid_sources[0x6c]	147534	1			T5	83		T7	251		T8	90
valid_sources[0x6d]	135327	1			T2	2		T5	86		T7	262
valid_sources[0x6e]	148076	1			T1	1		T5	69		T7	195
valid_sources[0x6f]	143402	1			T5	77		T7	269		T8	70
valid_sources[0x70]	141216	1			T5	67		T6	2		T7	238
valid_sources[0x71]	168956	1			T5	109		T7	258		T8	81
valid_sources[0x72]	138558	1			T5	69		T7	254		T8	69
valid_sources[0x73]	169140	1			T5	65		T7	246		T8	74
valid_sources[0x74]	156101	1			T1	3		T5	81		T7	222
valid_sources[0x75]	146210	1			T1	2		T5	90		T7	248
valid_sources[0x76]	141893	1			T5	45		T7	211		T8	85
valid_sources[0x77]	214851	1			T1	2		T5	80		T7	243
valid_sources[0x78]	153060	1			T5	84		T7	236		T8	89
valid_sources[0x79]	170960	1			T3	481		T5	61		T7	251
valid_sources[0x7a]	168647	1			T5	78		T7	273		T8	86
valid_sources[0x7b]	141721	1			T5	65		T7	233		T8	58
valid_sources[0x7c]	147129	1			T1	2		T5	88		T7	211
valid_sources[0x7d]	158411	1			T1	6		T5	72		T7	244
valid_sources[0x7e]	141091	1			T5	101		T7	256		T8	75
valid_sources[0x7f]	153520	1			T5	123		T7	295		T8	73
valid_sources[0x80]	139435	1			T5	71		T7	253		T8	87

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7284222

1

T1

7

T2

2

T3

60

values[0x0]

all_enables

biggest_size

211642

1

T1

16

T2

14

T3

29

values[0x1]

all_enables

biggest_size

146093

1

T1

11

T2

10

T3

15