Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	380594994	0	0	0
ctrl_rd_A	380594994	2163	0	0
host_fifo_config_rd_A	380594994	5236	0	0
host_nack_handler_timeout_rd_A	380594994	841	0	0
host_timeout_ctrl_rd_A	380594994	768	0	0
intr_enable_rd_A	380594994	4085	0	0
ovrd_rd_A	380594994	2051	0	0
target_fifo_config_rd_A	380594994	969	0	0
target_id_rd_A	380594994	1235	0	0
target_timeout_ctrl_rd_A	380594994	919	0	0
timeout_ctrl_rd_A	380594994	1061	0	0
timing0_rd_A	380594994	826	0	0
timing1_rd_A	380594994	936	0	0
timing2_rd_A	380594994	951	0	0
timing3_rd_A	380594994	940	0	0
timing4_rd_A	380594994	774	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	2163	0	0
T99	1224	31	0	0
T100	2160	13	0	0
T101	18792	93	0	0
T102	2860	70	0	0
T103	4367	18	0	0
T104	13705	362	0	0
T105	1784	29	0	0
T106	7812	26	0	0
T107	7417	167	0	0
T108	3075	48	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	5236	0	0
T24	156164	0	0	0
T80	299157	117	0	0
T109	0	104	0	0
T110	0	165	0	0
T111	0	146	0	0
T112	0	144	0	0
T113	0	72	0	0
T114	0	201	0	0
T115	0	238	0	0
T116	0	166	0	0
T117	0	148	0	0
T118	86570	0	0	0
T119	49875	0	0	0
T120	35878	0	0	0
T121	34498	0	0	0
T122	39594	0	0	0
T123	56001	0	0	0
T124	55100	0	0	0
T125	833	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	841	0	0
T99	1224	5	0	0
T100	2160	17	0	0
T101	18792	39	0	0
T102	2860	13	0	0
T104	13705	109	0	0
T107	7417	68	0	0
T108	3075	16	0	0
T126	2056	10	0	0
T127	1543	10	0	0
T128	13880	144	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	768	0	0
T100	2160	6	0	0
T101	18792	52	0	0
T102	2860	7	0	0
T103	4367	2	0	0
T104	13705	62	0	0
T105	1784	10	0	0
T106	7812	5	0	0
T107	7417	49	0	0
T108	3075	14	0	0
T126	2056	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	4085	0	0
T34	0	40	0	0
T99	0	5	0	0
T100	0	2	0	0
T101	0	224	0	0
T117	0	15	0	0
T129	721264	9	0	0
T130	0	13	0	0
T131	0	19	0	0
T132	0	5	0	0
T133	0	11	0	0
T134	26040	0	0	0
T135	17569	0	0	0
T136	347192	0	0	0
T137	191281	0	0	0
T138	44748	0	0	0
T139	217221	0	0	0
T140	168457	0	0	0
T141	69918	0	0	0
T142	213585	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	2051	0	0
T143	2735	52	0	0
T144	2745	38	0	0
T145	0	22	0	0
T146	0	70	0	0
T147	0	59	0	0
T148	0	50	0	0
T149	0	55	0	0
T150	0	40	0	0
T151	0	45	0	0
T152	0	57	0	0
T153	138233	0	0	0
T154	58375	0	0	0
T155	93225	0	0	0
T156	13428	0	0	0
T157	13635	0	0	0
T158	53948	0	0	0
T159	141609	0	0	0
T160	83725	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	969	0	0
T100	2160	9	0	0
T101	18792	52	0	0
T102	2860	5	0	0
T103	4367	3	0	0
T104	13705	123	0	0
T105	1784	6	0	0
T106	7812	13	0	0
T107	7417	79	0	0
T108	3075	24	0	0
T126	2056	13	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	1235	0	0
T99	1224	17	0	0
T100	2160	11	0	0
T101	18792	81	0	0
T102	2860	20	0	0
T103	4367	2	0	0
T104	13705	177	0	0
T106	7812	19	0	0
T107	7417	88	0	0
T108	3075	10	0	0
T126	2056	18	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	919	0	0
T99	1224	1	0	0
T100	2160	15	0	0
T101	18792	69	0	0
T102	2860	8	0	0
T104	13705	90	0	0
T105	1784	6	0	0
T106	7812	3	0	0
T107	7417	88	0	0
T108	3075	23	0	0
T126	2056	13	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	1061	0	0
T100	2160	12	0	0
T101	18792	64	0	0
T102	2860	15	0	0
T103	4367	1	0	0
T104	13705	118	0	0
T105	1784	13	0	0
T106	7812	21	0	0
T107	7417	136	0	0
T108	3075	20	0	0
T126	2056	24	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	826	0	0
T99	1224	4	0	0
T100	2160	9	0	0
T101	18792	54	0	0
T102	2860	5	0	0
T104	13705	138	0	0
T105	1784	6	0	0
T106	7812	9	0	0
T107	7417	58	0	0
T108	3075	15	0	0
T126	2056	12	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	936	0	0
T99	1224	2	0	0
T100	2160	10	0	0
T101	18792	49	0	0
T102	2860	14	0	0
T104	13705	119	0	0
T105	1784	6	0	0
T106	7812	11	0	0
T107	7417	88	0	0
T108	3075	25	0	0
T126	2056	2	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	951	0	0
T99	1224	2	0	0
T100	2160	17	0	0
T101	18792	57	0	0
T102	2860	14	0	0
T104	13705	115	0	0
T105	1784	3	0	0
T106	7812	16	0	0
T107	7417	55	0	0
T108	3075	29	0	0
T126	2056	3	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	940	0	0
T99	1224	5	0	0
T100	2160	3	0	0
T101	18792	91	0	0
T102	2860	11	0	0
T104	13705	113	0	0
T105	1784	4	0	0
T106	7812	7	0	0
T107	7417	50	0	0
T108	3075	16	0	0
T126	2056	15	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380594994	774	0	0
T99	1224	7	0	0
T100	2160	8	0	0
T101	18792	54	0	0
T102	2860	8	0	0
T104	13705	90	0	0
T105	1784	7	0	0
T106	7812	9	0	0
T107	7417	41	0	0
T108	3075	20	0	0
T126	2056	18	0	0