Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
85.71 85.71 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_rd_wr_cg 85.71 1 100 1 64 64



Group Instance : i2c_rd_wr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64



Summary for Group Instance i2c_rd_wr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 2 16 88.89
Crosses 24 4 20 83.33


Variables for Group Instance i2c_rd_wr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
address_match 2 0 2 100.00 100 1 1 2
cp_address_match 4 0 4 100.00 100 1 1 0
cp_read_byte 5 1 4 80.00 100 1 1 0
cp_write_byte 5 1 4 80.00 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0


Crosses for Group Instance i2c_rd_wr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_address_match_x_ip_mode 4 0 4 100.00 100 1 1 0
cross_write_byte_x_ip_mode 10 2 8 80.00 100 1 1 0
cross_read_byte_x_ip_mode 10 2 8 80.00 100 1 1 0


Summary for Variable address_match

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for address_match

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12320988 1 T2 1023 T4 16826 T9 311
auto[1] 12199945 1 T1 31322 T2 35 T4 1232


Summary for Variable cp_address_match

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_address_match

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_addr_no_match 4300428 1 T2 1017 T4 8905 T9 297
read_addr_match 6707951 1 T1 31303 T2 14 T4 609
write_addr_no_match 7701305 1 T4 7909 T10 7097 T45 1025
write_addr_match 5463717 1 T4 609 T5 32622 T6 6388


Summary for Variable cp_read_byte

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 1 4 80.00


User Defined Bins for cp_read_byte

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_one 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high 2238016 1 T1 6612 T2 177 T4 1907
med 4265143 1 T1 12229 T2 378 T4 3908
low 4381855 1 T1 12165 T2 460 T4 3619
all_zero 123365 1 T1 297 T2 16 T4 80


Summary for Variable cp_write_byte

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 1 4 80.00


User Defined Bins for cp_write_byte

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_one 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high 2659430 1 T4 1863 T5 6804 T6 1493
med 5113241 1 T4 3534 T5 13153 T6 2257
low 5262844 1 T4 3080 T5 12394 T6 2620
all_zero 129507 1 T4 41 T5 271 T6 18


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 12908111 1 T2 1058 T4 18058 T9 320
host 11612822 1 T1 31322 T5 32644 T6 7172


Summary for Cross cross_address_match_x_ip_mode

Samples crossed: address_match ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_address_match_x_ip_mode

Bins
address_matchip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] device 12316360 1 T2 1023 T4 16826 T9 311
auto[0] host 4628 1 T213 1 T233 1 T97 2
auto[1] device 591751 1 T2 35 T4 1232 T9 9
auto[1] host 11608194 1 T1 31322 T5 32644 T6 7172


Summary for Cross cross_write_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 2 8 80.00 2


Automatically Generated Cross Bins for cross_write_byte_x_ip_mode

Element holes
cp_write_byteip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[all_one] * -- -- 2


Covered bins
cp_write_byteip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high device 1618995 1 T4 1863 T10 1203 T45 165
high host 1040435 1 T5 6804 T6 1493 T30 703
med device 3123861 1 T4 3534 T10 2928 T45 401
med host 1989380 1 T5 13153 T6 2257 T8 9
low device 3242165 1 T4 3080 T10 2884 T45 529
low host 2020679 1 T5 12394 T6 2620 T8 75
all_zero device 77109 1 T4 41 T10 87 T63 10
all_zero host 52398 1 T5 271 T6 18 T30 22


Summary for Cross cross_read_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 2 8 80.00 2


Automatically Generated Cross Bins for cross_read_byte_x_ip_mode

Element holes
cp_write_byteip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[all_one] * -- -- 2


Covered bins
cp_write_byteip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
high device 1618995 1 T4 1863 T10 1203 T45 165
high host 1040435 1 T5 6804 T6 1493 T30 703
med device 3123861 1 T4 3534 T10 2928 T45 401
med host 1989380 1 T5 13153 T6 2257 T8 9
low device 3242165 1 T4 3080 T10 2884 T45 529
low host 2020679 1 T5 12394 T6 2620 T8 75
all_zero device 77109 1 T4 41 T10 87 T63 10
all_zero host 52398 1 T5 271 T6 18 T30 22

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