Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27637880	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7624635

1

T1

15417

T2

23

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34423119	1			T1	31645		T2	51		T3	1
values[0x0]	418579	1			T1	80		T2	33		T3	3
values[0x1]	420817	1			T1	105		T2	23		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19340528	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15921987

1

T1

18910

T2

44

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	129952	1			T1	109		T4	4		T5	203
valid_sources[0x01]	130013	1			T1	114		T4	9		T5	8
valid_sources[0x02]	145996	1			T1	147		T4	5		T5	5
valid_sources[0x03]	130064	1			T1	130		T4	4		T5	618
valid_sources[0x04]	126131	1			T1	129		T4	4		T5	26
valid_sources[0x05]	153907	1			T1	128		T4	2		T5	3
valid_sources[0x06]	139684	1			T1	136		T4	3		T5	8
valid_sources[0x07]	166906	1			T1	101		T4	3		T5	29
valid_sources[0x08]	138272	1			T1	134		T4	5		T5	9
valid_sources[0x09]	136957	1			T1	137		T4	7		T5	377
valid_sources[0x0a]	126783	1			T1	138		T4	8		T5	5
valid_sources[0x0b]	153792	1			T1	138		T4	11		T5	113
valid_sources[0x0c]	152467	1			T1	113		T4	6		T5	13
valid_sources[0x0d]	145739	1			T1	121		T4	4		T5	3
valid_sources[0x0e]	149034	1			T1	147		T4	6		T5	14
valid_sources[0x0f]	134694	1			T1	139		T4	4		T5	6
valid_sources[0x10]	118590	1			T1	145		T2	1		T4	5
valid_sources[0x11]	132030	1			T1	127		T4	7		T5	199
valid_sources[0x12]	120244	1			T1	118		T2	1		T4	13
valid_sources[0x13]	126737	1			T1	130		T4	6		T5	142
valid_sources[0x14]	141374	1			T1	132		T4	8		T5	5
valid_sources[0x15]	129970	1			T1	91		T4	5		T5	7
valid_sources[0x16]	135618	1			T1	115		T4	9		T5	6
valid_sources[0x17]	132347	1			T1	136		T2	22		T3	1
valid_sources[0x18]	142715	1			T1	109		T4	11		T5	11
valid_sources[0x19]	133901	1			T1	132		T4	5		T5	12
valid_sources[0x1a]	128379	1			T1	136		T4	5		T5	408
valid_sources[0x1b]	133403	1			T1	118		T4	5		T5	99
valid_sources[0x1c]	131716	1			T1	122		T4	7		T5	23
valid_sources[0x1d]	133915	1			T1	117		T4	2		T5	6
valid_sources[0x1e]	130043	1			T1	127		T4	10		T5	7
valid_sources[0x1f]	136189	1			T1	137		T4	10		T5	4
valid_sources[0x20]	126689	1			T1	123		T4	9		T5	2
valid_sources[0x21]	142487	1			T1	124		T4	13		T5	2
valid_sources[0x22]	133928	1			T1	119		T4	5		T5	2
valid_sources[0x23]	140048	1			T1	123		T4	11		T5	6
valid_sources[0x24]	136674	1			T1	109		T2	5		T4	6
valid_sources[0x25]	133942	1			T1	145		T2	4		T4	3
valid_sources[0x26]	148774	1			T1	113		T4	8		T5	4
valid_sources[0x27]	143360	1			T1	130		T4	3		T5	9
valid_sources[0x28]	129376	1			T1	129		T4	6		T5	16
valid_sources[0x29]	132713	1			T1	101		T4	5		T5	94
valid_sources[0x2a]	135381	1			T1	146		T4	4		T5	9
valid_sources[0x2b]	139931	1			T1	142		T4	10		T5	18
valid_sources[0x2c]	137722	1			T1	133		T4	7		T5	12
valid_sources[0x2d]	135010	1			T1	138		T4	12		T5	10
valid_sources[0x2e]	137982	1			T1	127		T4	4		T5	314
valid_sources[0x2f]	132773	1			T1	126		T4	7		T5	103
valid_sources[0x30]	130345	1			T1	143		T4	8		T5	11
valid_sources[0x31]	137107	1			T1	122		T4	3		T5	5
valid_sources[0x32]	133304	1			T1	124		T4	5		T5	13
valid_sources[0x33]	148091	1			T1	124		T4	9		T5	13
valid_sources[0x34]	128342	1			T1	114		T3	1		T4	3
valid_sources[0x35]	135510	1			T1	107		T4	8		T5	113
valid_sources[0x36]	124419	1			T1	110		T4	5		T5	203
valid_sources[0x37]	126787	1			T1	151		T4	5		T5	11
valid_sources[0x38]	147247	1			T1	121		T4	6		T5	104
valid_sources[0x39]	126171	1			T1	115		T4	7		T5	6
valid_sources[0x3a]	135815	1			T1	120		T4	10		T5	16
valid_sources[0x3b]	128417	1			T1	98		T4	6		T5	11
valid_sources[0x3c]	125698	1			T1	124		T4	5		T5	6
valid_sources[0x3d]	146731	1			T1	112		T4	4		T5	26
valid_sources[0x3e]	136103	1			T1	138		T2	1		T4	6
valid_sources[0x3f]	130657	1			T1	129		T4	6		T5	1
valid_sources[0x40]	137929	1			T1	122		T4	4		T5	103
valid_sources[0x41]	130884	1			T1	116		T4	5		T5	8
valid_sources[0x42]	126551	1			T1	130		T4	1		T5	12
valid_sources[0x43]	132280	1			T1	132		T4	10		T5	13
valid_sources[0x44]	134864	1			T1	143		T2	2		T4	5
valid_sources[0x45]	131928	1			T1	149		T4	8		T5	99
valid_sources[0x46]	149852	1			T1	143		T4	4		T5	679
valid_sources[0x47]	124132	1			T1	124		T4	5		T5	5
valid_sources[0x48]	130092	1			T1	127		T4	6		T5	10
valid_sources[0x49]	122527	1			T1	106		T4	2		T5	3
valid_sources[0x4a]	128973	1			T1	119		T4	5		T5	5
valid_sources[0x4b]	125527	1			T1	129		T4	6		T5	15
valid_sources[0x4c]	128649	1			T1	126		T2	3		T4	5
valid_sources[0x4d]	129073	1			T1	120		T4	6		T5	6
valid_sources[0x4e]	152588	1			T1	120		T4	5		T5	1386
valid_sources[0x4f]	137614	1			T1	124		T4	4		T5	25
valid_sources[0x50]	134457	1			T1	129		T4	17		T5	214
valid_sources[0x51]	133915	1			T1	135		T2	1		T4	6
valid_sources[0x52]	136847	1			T1	118		T4	4		T5	5
valid_sources[0x53]	124350	1			T1	133		T4	4		T5	620
valid_sources[0x54]	135706	1			T1	125		T4	2		T5	5
valid_sources[0x55]	133589	1			T1	125		T4	4		T5	8
valid_sources[0x56]	139454	1			T1	109		T4	2		T5	719
valid_sources[0x57]	137156	1			T1	112		T4	6		T5	21
valid_sources[0x58]	141052	1			T1	102		T4	12		T5	787
valid_sources[0x59]	129615	1			T1	135		T4	10		T5	12
valid_sources[0x5a]	139001	1			T1	117		T4	6		T5	4
valid_sources[0x5b]	142169	1			T1	106		T4	2		T5	1442
valid_sources[0x5c]	142429	1			T1	113		T2	2		T4	6
valid_sources[0x5d]	129295	1			T1	110		T4	4		T5	7
valid_sources[0x5e]	149567	1			T1	126		T4	7		T5	5
valid_sources[0x5f]	148134	1			T1	121		T4	5		T5	95
valid_sources[0x60]	129578	1			T1	137		T4	8		T5	11
valid_sources[0x61]	136738	1			T1	129		T4	8		T5	12
valid_sources[0x62]	136894	1			T1	126		T4	5		T5	5
valid_sources[0x63]	155267	1			T1	104		T4	9		T5	3
valid_sources[0x64]	122553	1			T1	121		T4	4		T5	412
valid_sources[0x65]	126905	1			T1	129		T3	1		T4	4
valid_sources[0x66]	132335	1			T1	126		T4	10		T5	9
valid_sources[0x67]	195263	1			T1	120		T4	8		T6	76
valid_sources[0x68]	137773	1			T1	137		T4	8		T5	4
valid_sources[0x69]	131806	1			T1	127		T4	5		T5	4
valid_sources[0x6a]	138019	1			T1	111		T4	2		T5	289
valid_sources[0x6b]	143318	1			T1	119		T4	8		T5	836
valid_sources[0x6c]	128803	1			T1	109		T4	4		T5	504
valid_sources[0x6d]	126183	1			T1	146		T4	8		T5	9
valid_sources[0x6e]	136435	1			T1	121		T4	4		T5	216
valid_sources[0x6f]	136725	1			T1	123		T4	9		T5	417
valid_sources[0x70]	136865	1			T1	119		T4	6		T5	7
valid_sources[0x71]	124668	1			T1	97		T4	2		T5	189
valid_sources[0x72]	121364	1			T1	112		T4	2		T5	12
valid_sources[0x73]	149149	1			T1	136		T4	2		T5	7
valid_sources[0x74]	144598	1			T1	117		T4	12		T5	4
valid_sources[0x75]	131727	1			T1	120		T4	1		T5	114
valid_sources[0x76]	130524	1			T1	141		T4	4		T5	9
valid_sources[0x77]	137228	1			T1	113		T4	8		T5	11
valid_sources[0x78]	136837	1			T1	114		T4	5		T5	10
valid_sources[0x79]	137618	1			T1	116		T4	1		T5	5
valid_sources[0x7a]	138124	1			T1	144		T4	11		T5	1
valid_sources[0x7b]	139208	1			T1	116		T4	5		T5	20
valid_sources[0x7c]	128823	1			T1	114		T4	4		T5	14
valid_sources[0x7d]	135532	1			T1	125		T4	1		T5	17
valid_sources[0x7e]	144385	1			T1	126		T4	6		T5	14
valid_sources[0x7f]	129017	1			T1	119		T4	3		T5	2
valid_sources[0x80]	131272	1			T1	110		T3	1		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7249914

1

T1

15264

T2

4

T3

1

values[0x0]

all_enables

biggest_size

221731

1

T1

68

T2

16

T4

96

values[0x1]

all_enables

biggest_size

152990

1

T1

85

T2

3

T3

1