Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	431283996	0	0	0
ctrl_rd_A	431283996	1948	0	0
host_fifo_config_rd_A	431283996	3833	0	0
host_nack_handler_timeout_rd_A	431283996	1237	0	0
host_timeout_ctrl_rd_A	431283996	991	0	0
intr_enable_rd_A	431283996	3106	0	0
ovrd_rd_A	431283996	2145	0	0
target_fifo_config_rd_A	431283996	1142	0	0
target_id_rd_A	431283996	1370	0	0
target_timeout_ctrl_rd_A	431283996	1131	0	0
timeout_ctrl_rd_A	431283996	1225	0	0
timing0_rd_A	431283996	1103	0	0
timing1_rd_A	431283996	1249	0	0
timing2_rd_A	431283996	1253	0	0
timing3_rd_A	431283996	1127	0	0
timing4_rd_A	431283996	1083	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1948	0	0
T94	2624	31	0	0
T95	3681	14	0	0
T96	2359	26	0	0
T97	12830	156	0	0
T98	13229	220	0	0
T99	12905	12	0	0
T100	2663	71	0	0
T101	3405	2	0	0
T102	8733	53	0	0
T103	2674	22	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	3833	0	0
T65	82603	0	0	0
T76	125578	0	0	0
T80	440497	164	0	0
T104	0	209	0	0
T105	0	107	0	0
T106	0	104	0	0
T107	0	68	0	0
T108	0	163	0	0
T109	0	252	0	0
T110	0	146	0	0
T111	0	127	0	0
T112	0	203	0	0
T113	14955	0	0	0
T114	41058	0	0	0
T115	385664	0	0	0
T116	135434	0	0	0
T117	6458	0	0	0
T118	30490	0	0	0
T119	300038	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1237	0	0
T94	2624	15	0	0
T95	3681	24	0	0
T96	2359	9	0	0
T97	12830	71	0	0
T98	13229	86	0	0
T99	12905	2	0	0
T100	2663	22	0	0
T102	8733	10	0	0
T103	2674	7	0	0
T120	4111	34	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	991	0	0
T94	2624	10	0	0
T95	3681	19	0	0
T96	2359	9	0	0
T97	12830	40	0	0
T98	13229	40	0	0
T99	12905	23	0	0
T100	2663	16	0	0
T101	3405	14	0	0
T102	8733	18	0	0
T103	2674	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	3106	0	0
T94	0	6	0	0
T95	0	55	0	0
T96	0	72	0	0
T97	0	354	0	0
T98	0	502	0	0
T121	188586	38	0	0
T122	0	17	0	0
T123	0	39	0	0
T124	0	25	0	0
T125	0	27	0	0
T126	133657	0	0	0
T127	24238	0	0	0
T128	146149	0	0	0
T129	15733	0	0	0
T130	13459	0	0	0
T131	1861	0	0	0
T132	18477	0	0	0
T133	7835	0	0	0
T134	116818	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	2145	0	0
T36	401465	0	0	0
T43	192292	0	0	0
T48	49019	0	0	0
T54	50970	0	0	0
T56	363728	0	0	0
T58	8639	0	0	0
T75	2112	4	0	0
T78	15232	0	0	0
T131	0	34	0	0
T135	0	42	0	0
T136	0	28	0	0
T137	0	58	0	0
T138	0	35	0	0
T139	0	74	0	0
T140	0	55	0	0
T141	0	11	0	0
T142	0	40	0	0
T143	41878	0	0	0
T144	6827	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1142	0	0
T94	2624	6	0	0
T95	3681	24	0	0
T96	2359	14	0	0
T97	12830	82	0	0
T98	13229	53	0	0
T99	12905	18	0	0
T100	2663	17	0	0
T101	3405	15	0	0
T102	8733	12	0	0
T103	2674	15	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1370	0	0
T94	2624	16	0	0
T95	3681	34	0	0
T96	2359	3	0	0
T97	12830	67	0	0
T98	13229	134	0	0
T99	12905	6	0	0
T100	2663	16	0	0
T101	3405	2	0	0
T102	8733	15	0	0
T103	2674	2	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1131	0	0
T94	2624	9	0	0
T95	3681	16	0	0
T96	2359	8	0	0
T97	12830	58	0	0
T98	13229	61	0	0
T99	12905	18	0	0
T100	2663	17	0	0
T101	3405	11	0	0
T102	8733	6	0	0
T103	2674	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1225	0	0
T94	2624	8	0	0
T95	3681	15	0	0
T96	2359	7	0	0
T97	12830	47	0	0
T98	13229	143	0	0
T99	12905	18	0	0
T100	2663	12	0	0
T101	3405	24	0	0
T102	8733	12	0	0
T103	2674	10	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1103	0	0
T94	2624	1	0	0
T95	3681	21	0	0
T96	2359	6	0	0
T97	12830	89	0	0
T98	13229	62	0	0
T99	12905	8	0	0
T100	2663	19	0	0
T101	3405	7	0	0
T102	8733	13	0	0
T103	2674	7	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1249	0	0
T94	2624	10	0	0
T95	3681	33	0	0
T96	2359	3	0	0
T97	12830	105	0	0
T98	13229	66	0	0
T99	12905	23	0	0
T100	2663	18	0	0
T101	3405	6	0	0
T102	8733	38	0	0
T103	2674	2	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1253	0	0
T94	2624	9	0	0
T95	3681	27	0	0
T96	2359	12	0	0
T97	12830	53	0	0
T98	13229	76	0	0
T99	12905	16	0	0
T100	2663	30	0	0
T101	3405	7	0	0
T102	8733	30	0	0
T103	2674	21	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1127	0	0
T94	2624	17	0	0
T95	3681	19	0	0
T96	2359	14	0	0
T97	12830	66	0	0
T98	13229	75	0	0
T99	12905	11	0	0
T100	2663	18	0	0
T101	3405	1	0	0
T102	8733	34	0	0
T103	2674	9	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431283996	1083	0	0
T94	2624	8	0	0
T95	3681	26	0	0
T96	2359	3	0	0
T97	12830	45	0	0
T98	13229	52	0	0
T100	2663	25	0	0
T101	3405	16	0	0
T102	8733	30	0	0
T103	2674	22	0	0
T120	4111	25	0	0