Unified Coverage Report :: Group :: tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg

Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	85.71	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_rd_wr_cg	85.71	1	100	1	64	64

---

Group Instance : i2c_rd_wr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance i2c_rd_wr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	24	4	20	83.33

Variables for Group Instance i2c_rd_wr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
address_match	2	0	2	100.00	100	1	1	2
cp_address_match	4	0	4	100.00	100	1	1	0
cp_read_byte	5	1	4	80.00	100	1	1	0
cp_write_byte	5	1	4	80.00	100	1	1	0
ip_mode_cp	2	0	2	100.00	100	1	1	0

Crosses for Group Instance i2c_rd_wr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_address_match_x_ip_mode	4	0	4	100.00	100	1	1	0
cross_write_byte_x_ip_mode	10	2	8	80.00	100	1	1	0
cross_read_byte_x_ip_mode	10	2	8	80.00	100	1	1	0

Summary for Variable address_match

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for address_match

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12254286

1

T1

581

T2

15312

T3

493

auto[1]

10155660

1

T1

7

T2

216

T3

7

---

Summary for Variable cp_address_match

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_address_match

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_addr_no_match	4190142	1			T2	7494		T7	3920		T8	382
read_addr_match	5493953	1			T2	99		T5	20021		T6	1370
write_addr_no_match	7778231	1			T1	557		T2	7796		T3	475
write_addr_match	4633798	1			T1	5		T2	116		T3	5

---

Summary for Variable cp_read_byte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_read_byte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_one	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	1972514	1			T2	1519		T5	3948		T6	32
med	3750390	1			T2	2909		T5	7575		T6	1192
low	3852057	1			T2	3112		T5	8405		T6	139
all_zero	109134	1			T2	53		T5	93		T6	7

---

Summary for Variable cp_write_byte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_write_byte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_one	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	2504052	1			T1	46		T2	1498		T3	134
med	4845136	1			T1	132		T2	3232		T3	172
low	4936355	1			T1	369		T2	3098		T3	152
all_zero	126486	1			T1	15		T2	84		T3	22

---

Summary for Variable ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for ip_mode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

device

12947510

1

T1

588

T2

15528

T3

500

host

9462436

1

T5

37660

T6

1697

T14

61726

---

Summary for Cross cross_address_match_x_ip_mode

Samples crossed: address_match ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_address_match_x_ip_mode

Bins

address_match

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

device

12254167

1

T1

581

T2

15312

T3

493

auto[0]

host

119

1

T178

5

T92

3

T220

1

auto[1]

device

693343

1

T1

7

T2

216

T3

7

auto[1]

host

9462317

1

T5

37660

T6

1697

T14

61726

---

Summary for Cross cross_write_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	2	8	80.00	2

Automatically Generated Cross Bins for cross_write_byte_x_ip_mode

Element holes

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[all_one]	*	--	--	2

Covered bins

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	device	1647476	1			T1	46		T2	1498		T3	134
high	host	856576	1			T5	3578		T6	36		T14	6436
med	device	3194370	1			T1	132		T2	3232		T3	172
med	host	1650766	1			T5	6233		T6	112		T14	11694
low	device	3289649	1			T1	369		T2	3098		T3	152
low	host	1646706	1			T5	7627		T6	34		T14	10435
all_zero	device	80781	1			T1	15		T2	84		T3	22
all_zero	host	45705	1			T5	181		T6	21		T14	211

---

Summary for Cross cross_read_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	2	8	80.00	2

Automatically Generated Cross Bins for cross_read_byte_x_ip_mode

Element holes

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[all_one]	*	--	--	2

Covered bins

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	device	1647476	1			T1	46		T2	1498		T3	134
high	host	856576	1			T5	3578		T6	36		T14	6436
med	device	3194370	1			T1	132		T2	3232		T3	172
med	host	1650766	1			T5	6233		T6	112		T14	11694
low	device	3289649	1			T1	369		T2	3098		T3	152
low	host	1646706	1			T5	7627		T6	34		T14	10435
all_zero	device	80781	1			T1	15		T2	84		T3	22
all_zero	host	45705	1			T5	181		T6	21		T14	211