Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31384121	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8122378

1

T1

17

T2

247

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38655768	1			T1	10		T2	12777		T3	20
values[0x0]	425328	1			T1	11		T2	176		T3	12
values[0x1]	425403	1			T1	7		T2	163		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21854718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17651781

1

T1

20

T2

6491

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	161251	1			T2	61		T3	2		T5	123
valid_sources[0x01]	147331	1			T2	48		T5	98		T6	31
valid_sources[0x02]	146755	1			T2	62		T5	108		T6	18
valid_sources[0x03]	165211	1			T2	50		T3	1		T5	105
valid_sources[0x04]	155763	1			T1	3		T2	51		T5	136
valid_sources[0x05]	148098	1			T1	1		T2	32		T5	106
valid_sources[0x06]	161170	1			T2	60		T5	141		T6	39
valid_sources[0x07]	163228	1			T2	43		T5	117		T6	23
valid_sources[0x08]	145664	1			T2	61		T5	103		T6	22
valid_sources[0x09]	158881	1			T2	63		T5	95		T6	23
valid_sources[0x0a]	145891	1			T2	51		T5	120		T6	30
valid_sources[0x0b]	149888	1			T2	51		T5	88		T6	12
valid_sources[0x0c]	143776	1			T2	47		T3	1		T5	86
valid_sources[0x0d]	166255	1			T2	50		T5	132		T6	19
valid_sources[0x0e]	188619	1			T2	36		T3	1		T5	115
valid_sources[0x0f]	150315	1			T2	57		T5	119		T6	23
valid_sources[0x10]	160996	1			T2	52		T5	109		T6	18
valid_sources[0x11]	150637	1			T2	59		T5	138		T6	40
valid_sources[0x12]	149289	1			T2	44		T5	126		T6	31
valid_sources[0x13]	148129	1			T1	1		T2	55		T5	78
valid_sources[0x14]	148029	1			T2	43		T3	1		T5	134
valid_sources[0x15]	153073	1			T2	46		T5	117		T6	19
valid_sources[0x16]	160514	1			T2	53		T5	105		T6	18
valid_sources[0x17]	149998	1			T1	2		T2	46		T5	106
valid_sources[0x18]	156626	1			T2	47		T5	146		T6	12
valid_sources[0x19]	158015	1			T2	45		T5	142		T6	33
valid_sources[0x1a]	151722	1			T2	53		T5	126		T6	34
valid_sources[0x1b]	174296	1			T2	59		T5	98		T6	16
valid_sources[0x1c]	167000	1			T2	46		T3	1		T5	140
valid_sources[0x1d]	142669	1			T2	61		T5	113		T6	31
valid_sources[0x1e]	158737	1			T2	55		T5	100		T6	17
valid_sources[0x1f]	169910	1			T2	58		T3	2		T5	126
valid_sources[0x20]	171081	1			T2	52		T5	89		T6	36
valid_sources[0x21]	148401	1			T2	64		T3	1		T5	111
valid_sources[0x22]	155078	1			T2	54		T5	118		T6	32
valid_sources[0x23]	147705	1			T2	50		T5	79		T6	22
valid_sources[0x24]	152396	1			T2	56		T5	116		T6	41
valid_sources[0x25]	147648	1			T2	63		T5	109		T6	30
valid_sources[0x26]	149612	1			T2	41		T5	134		T6	31
valid_sources[0x27]	168065	1			T2	61		T3	1		T5	127
valid_sources[0x28]	143474	1			T2	44		T5	77		T6	19
valid_sources[0x29]	178521	1			T2	51		T5	139		T6	27
valid_sources[0x2a]	161654	1			T2	54		T5	109		T6	35
valid_sources[0x2b]	146588	1			T2	53		T5	110		T6	43
valid_sources[0x2c]	154243	1			T2	46		T5	118		T6	25
valid_sources[0x2d]	151858	1			T2	47		T5	88		T6	42
valid_sources[0x2e]	161397	1			T2	54		T5	87		T6	15
valid_sources[0x2f]	144265	1			T2	41		T5	104		T6	29
valid_sources[0x30]	150304	1			T2	49		T5	103		T6	23
valid_sources[0x31]	164415	1			T2	59		T5	119		T6	28
valid_sources[0x32]	149633	1			T2	48		T5	122		T6	27
valid_sources[0x33]	148405	1			T2	62		T5	101		T6	15
valid_sources[0x34]	157841	1			T2	64		T5	113		T6	25
valid_sources[0x35]	159797	1			T2	46		T5	118		T6	20
valid_sources[0x36]	149030	1			T2	52		T5	105		T6	21
valid_sources[0x37]	148933	1			T2	48		T5	89		T6	25
valid_sources[0x38]	150453	1			T2	66		T5	119		T6	57
valid_sources[0x39]	152338	1			T2	47		T3	1		T5	134
valid_sources[0x3a]	157961	1			T2	49		T5	113		T6	48
valid_sources[0x3b]	190881	1			T2	39		T5	117		T6	28
valid_sources[0x3c]	169655	1			T2	50		T5	132		T6	23
valid_sources[0x3d]	177653	1			T2	56		T5	90		T6	14
valid_sources[0x3e]	151709	1			T2	38		T4	1000		T5	130
valid_sources[0x3f]	151084	1			T2	40		T5	123		T6	22
valid_sources[0x40]	155341	1			T2	36		T5	128		T6	27
valid_sources[0x41]	149003	1			T2	44		T5	131		T6	21
valid_sources[0x42]	157290	1			T2	56		T5	110		T6	20
valid_sources[0x43]	149082	1			T2	46		T5	121		T6	16
valid_sources[0x44]	150542	1			T2	45		T3	1		T5	104
valid_sources[0x45]	159424	1			T2	56		T5	97		T6	20
valid_sources[0x46]	160740	1			T2	53		T5	112		T6	36
valid_sources[0x47]	149885	1			T2	53		T5	150		T6	25
valid_sources[0x48]	139641	1			T2	47		T5	114		T6	19
valid_sources[0x49]	157046	1			T2	45		T5	86		T6	21
valid_sources[0x4a]	154135	1			T2	43		T3	1		T5	104
valid_sources[0x4b]	138544	1			T2	58		T5	123		T6	29
valid_sources[0x4c]	150951	1			T2	49		T5	147		T6	26
valid_sources[0x4d]	152467	1			T2	47		T5	108		T6	14
valid_sources[0x4e]	155933	1			T2	54		T5	97		T6	36
valid_sources[0x4f]	158159	1			T2	54		T5	102		T6	27
valid_sources[0x50]	158269	1			T2	50		T5	97		T6	22
valid_sources[0x51]	157088	1			T2	48		T3	1		T5	109
valid_sources[0x52]	141764	1			T2	47		T3	1		T5	108
valid_sources[0x53]	148669	1			T2	55		T5	113		T6	25
valid_sources[0x54]	141829	1			T1	1		T2	53		T5	119
valid_sources[0x55]	149686	1			T2	49		T5	111		T6	23
valid_sources[0x56]	163138	1			T2	54		T5	120		T6	52
valid_sources[0x57]	146710	1			T2	58		T5	93		T6	13
valid_sources[0x58]	148153	1			T1	1		T2	59		T5	117
valid_sources[0x59]	146082	1			T2	61		T5	164		T6	43
valid_sources[0x5a]	169630	1			T2	39		T3	2		T5	110
valid_sources[0x5b]	138319	1			T2	43		T5	139		T6	17
valid_sources[0x5c]	145781	1			T2	43		T3	1		T5	119
valid_sources[0x5d]	160421	1			T2	52		T5	122		T6	9
valid_sources[0x5e]	168870	1			T1	1		T2	47		T3	2
valid_sources[0x5f]	142848	1			T2	39		T5	107		T6	30
valid_sources[0x60]	154526	1			T2	61		T5	105		T6	20
valid_sources[0x61]	157111	1			T2	48		T5	84		T6	34
valid_sources[0x62]	158003	1			T2	54		T3	2		T5	111
valid_sources[0x63]	144344	1			T2	52		T5	90		T6	28
valid_sources[0x64]	148953	1			T2	53		T5	106		T6	20
valid_sources[0x65]	153551	1			T2	53		T5	133		T6	31
valid_sources[0x66]	157658	1			T2	51		T5	109		T6	32
valid_sources[0x67]	150730	1			T2	55		T5	89		T6	32
valid_sources[0x68]	159507	1			T2	51		T5	127		T6	15
valid_sources[0x69]	145038	1			T2	48		T5	102		T6	22
valid_sources[0x6a]	143264	1			T2	41		T5	84		T6	26
valid_sources[0x6b]	155033	1			T2	42		T5	117		T6	21
valid_sources[0x6c]	149535	1			T2	53		T5	126		T6	24
valid_sources[0x6d]	154165	1			T2	57		T5	111		T6	10
valid_sources[0x6e]	151439	1			T1	1		T2	48		T5	98
valid_sources[0x6f]	148364	1			T2	53		T3	2		T5	91
valid_sources[0x70]	150471	1			T2	51		T5	121		T6	24
valid_sources[0x71]	156638	1			T2	63		T5	116		T6	28
valid_sources[0x72]	155299	1			T2	58		T5	95		T6	31
valid_sources[0x73]	165578	1			T2	61		T5	111		T6	33
valid_sources[0x74]	157848	1			T2	67		T5	126		T6	28
valid_sources[0x75]	160932	1			T1	2		T2	46		T3	1
valid_sources[0x76]	152455	1			T2	35		T3	1		T5	122
valid_sources[0x77]	174978	1			T2	65		T3	1		T5	133
valid_sources[0x78]	151675	1			T2	53		T5	121		T6	20
valid_sources[0x79]	158378	1			T1	1		T2	45		T5	129
valid_sources[0x7a]	145479	1			T2	42		T5	84		T6	26
valid_sources[0x7b]	148321	1			T2	62		T5	126		T6	28
valid_sources[0x7c]	149114	1			T2	52		T5	136		T6	19
valid_sources[0x7d]	151228	1			T2	61		T5	110		T6	26
valid_sources[0x7e]	150757	1			T2	45		T5	128		T6	31
valid_sources[0x7f]	153817	1			T2	37		T5	110		T6	28
valid_sources[0x80]	152190	1			T2	42		T5	79		T6	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7750085

1

T1

5

T2

150

T3

10

values[0x0]

all_enables

biggest_size

222260

1

T1

8

T2

67

T3

12

values[0x1]

all_enables

biggest_size

150033

1

T1

4

T2

30

T3

5