SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.b2b_txn_host_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
i2c_env_pkg.b2b_txn_target_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
b2b_read_different_addr | 1907 | 1 | T5 | 5 | T14 | 3 | T42 | 3 | ||||
b2b_read_same_addr | 323 | 1 | T5 | 1 | T20 | 9 | T135 | 4 | ||||
write_after_read_different_addr | 1835 | 1 | T5 | 7 | T14 | 10 | T42 | 4 | ||||
write_after_read_same_addr | 30 | 1 | T86 | 1 | T32 | 1 | T23 | 1 | ||||
read_after_write_different_addr | 1837 | 1 | T5 | 7 | T14 | 11 | T42 | 4 | ||||
read_after_write_same_addr | 31 | 1 | T31 | 1 | T101 | 1 | T267 | 1 | ||||
b2b_write_different_addr | 1861 | 1 | T5 | 1 | T14 | 11 | T42 | 7 | ||||
b2b_write_same_addr | 309 | 1 | T20 | 1 | T135 | 4 | T39 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
b2b_read_different_addr | 5507 | 1 | T2 | 16 | T55 | 26 | T132 | 25 | ||||
b2b_read_same_addr | 13125 | 1 | T2 | 19 | T4 | 12 | T7 | 27 | ||||
write_after_read_different_addr | 5708 | 1 | T4 | 8 | T8 | 1 | T9 | 5 | ||||
write_after_read_same_addr | 86 | 1 | T268 | 2 | T269 | 17 | T270 | 1 | ||||
read_after_write_different_addr | 5705 | 1 | T4 | 8 | T8 | 1 | T9 | 6 | ||||
read_after_write_same_addr | 90 | 1 | T271 | 1 | T268 | 2 | T269 | 19 | ||||
b2b_write_different_addr | 5391 | 1 | T9 | 10 | T46 | 49 | T47 | 6 | ||||
b2b_write_same_addr | 13086 | 1 | T4 | 24 | T8 | 2 | T9 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |