Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	402881014	0	0	0
ctrl_rd_A	402881014	2111	0	0
host_fifo_config_rd_A	402881014	3700	0	0
host_nack_handler_timeout_rd_A	402881014	1240	0	0
host_timeout_ctrl_rd_A	402881014	921	0	0
intr_enable_rd_A	402881014	3545	0	0
ovrd_rd_A	402881014	2189	0	0
target_fifo_config_rd_A	402881014	1209	0	0
target_id_rd_A	402881014	1584	0	0
target_timeout_ctrl_rd_A	402881014	1219	0	0
timeout_ctrl_rd_A	402881014	1470	0	0
timing0_rd_A	402881014	1320	0	0
timing1_rd_A	402881014	1344	0	0
timing2_rd_A	402881014	1191	0	0
timing3_rd_A	402881014	1178	0	0
timing4_rd_A	402881014	1268	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	2111	0	0
T91	2233	20	0	0
T92	7188	138	0	0
T93	3283	29	0	0
T94	5996	19	0	0
T95	2946	64	0	0
T96	3710	40	0	0
T97	6385	36	0	0
T98	7705	16	0	0
T99	1904	12	0	0
T100	6129	118	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	3700	0	0
T5	301488	106	0	0
T6	21144	0	0	0
T7	36278	0	0	0
T8	94008	0	0	0
T9	56656	0	0	0
T10	150806	0	0	0
T14	507152	217	0	0
T42	36714	0	0	0
T46	135054	0	0	0
T47	12753	0	0	0
T79	0	248	0	0
T101	0	169	0	0
T102	0	143	0	0
T103	0	204	0	0
T104	0	231	0	0
T105	0	62	0	0
T106	0	226	0	0
T107	0	117	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	1240	0	0
T91	2233	15	0	0
T92	7188	66	0	0
T93	3283	14	0	0
T94	5996	39	0	0
T95	2946	6	0	0
T96	3710	20	0	0
T97	6385	41	0	0
T98	7705	16	0	0
T99	1904	21	0	0
T100	6129	104	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	921	0	0
T92	7188	15	0	0
T93	3283	20	0	0
T94	5996	35	0	0
T95	2946	12	0	0
T96	3710	24	0	0
T97	6385	86	0	0
T98	7705	15	0	0
T99	1904	11	0	0
T100	6129	116	0	0
T108	3930	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	3545	0	0
T91	0	56	0	0
T92	0	215	0	0
T93	0	19	0	0
T94	0	74	0	0
T95	0	60	0	0
T96	0	59	0	0
T109	704045	5	0	0
T110	0	7	0	0
T111	0	21	0	0
T112	0	32	0	0
T113	85428	0	0	0
T114	263493	0	0	0
T115	57519	0	0	0
T116	20283	0	0	0
T117	12033	0	0	0
T118	12916	0	0	0
T119	13247	0	0	0
T120	122029	0	0	0
T121	960917	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	2189	0	0
T20	258861	0	0	0
T30	381288	0	0	0
T49	343221	0	0	0
T63	150484	0	0	0
T71	1986	47	0	0
T85	2774	0	0	0
T122	0	13	0	0
T123	0	49	0	0
T124	0	68	0	0
T125	0	43	0	0
T126	0	58	0	0
T127	0	29	0	0
T128	0	81	0	0
T129	0	47	0	0
T130	0	97	0	0
T131	55900	0	0	0
T132	108103	0	0	0
T133	205933	0	0	0
T134	1122	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	1209	0	0
T91	2233	13	0	0
T92	7188	47	0	0
T93	3283	13	0	0
T94	5996	19	0	0
T95	2946	16	0	0
T96	3710	22	0	0
T97	6385	45	0	0
T98	7705	12	0	0
T99	1904	12	0	0
T100	6129	123	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	1584	0	0
T91	2233	21	0	0
T92	7188	88	0	0
T93	3283	3	0	0
T94	5996	16	0	0
T95	2946	28	0	0
T96	3710	41	0	0
T97	6385	41	0	0
T98	7705	31	0	0
T99	1904	26	0	0
T100	6129	115	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	1219	0	0
T91	2233	11	0	0
T92	7188	56	0	0
T93	3283	20	0	0
T94	5996	36	0	0
T95	2946	35	0	0
T96	3710	26	0	0
T97	6385	21	0	0
T98	7705	12	0	0
T99	1904	9	0	0
T100	6129	108	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	1470	0	0
T91	2233	11	0	0
T92	7188	65	0	0
T93	3283	36	0	0
T94	5996	37	0	0
T95	2946	24	0	0
T96	3710	14	0	0
T97	6385	12	0	0
T98	7705	25	0	0
T99	1904	14	0	0
T100	6129	128	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	1320	0	0
T91	2233	2	0	0
T92	7188	77	0	0
T93	3283	10	0	0
T94	5996	56	0	0
T95	2946	9	0	0
T96	3710	29	0	0
T97	6385	66	0	0
T98	7705	21	0	0
T99	1904	8	0	0
T100	6129	94	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	1344	0	0
T91	2233	9	0	0
T92	7188	50	0	0
T93	3283	6	0	0
T94	5996	42	0	0
T95	2946	29	0	0
T96	3710	29	0	0
T97	6385	95	0	0
T98	7705	12	0	0
T99	1904	16	0	0
T100	6129	115	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	1191	0	0
T91	2233	4	0	0
T92	7188	48	0	0
T93	3283	7	0	0
T94	5996	12	0	0
T95	2946	19	0	0
T96	3710	11	0	0
T97	6385	35	0	0
T98	7705	18	0	0
T99	1904	2	0	0
T100	6129	113	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	1178	0	0
T91	2233	7	0	0
T92	7188	46	0	0
T93	3283	23	0	0
T94	5996	18	0	0
T95	2946	29	0	0
T96	3710	28	0	0
T97	6385	31	0	0
T98	7705	10	0	0
T99	1904	14	0	0
T100	6129	116	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402881014	1268	0	0
T91	2233	6	0	0
T92	7188	74	0	0
T93	3283	10	0	0
T94	5996	35	0	0
T95	2946	15	0	0
T96	3710	23	0	0
T97	6385	47	0	0
T98	7705	5	0	0
T99	1904	12	0	0
T100	6129	141	0	0