Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36766305	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10002109

1

T1

970

T2

323

T3

1737

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	45940201	1			T1	2594		T2	906		T3	3454
values[0x0]	413167	1			T1	51		T2	183		T3	135
values[0x1]	415046	1			T1	56		T2	225		T3	145

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25707286	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21061128

1

T1

1443

T2

577

T3

2157

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	194874	1			T1	9		T3	13		T6	40
valid_sources[0x01]	179639	1			T1	11		T6	48		T7	1
valid_sources[0x02]	185981	1			T1	9		T6	37		T7	5
valid_sources[0x03]	193821	1			T1	3		T3	6		T6	41
valid_sources[0x04]	180373	1			T1	2		T6	36		T7	8
valid_sources[0x05]	177225	1			T6	47		T7	5		T8	497
valid_sources[0x06]	171329	1			T4	80		T6	37		T7	7
valid_sources[0x07]	190736	1			T1	1		T3	23		T6	54
valid_sources[0x08]	187695	1			T1	24		T6	48		T7	8
valid_sources[0x09]	165126	1			T1	1		T6	44		T7	6
valid_sources[0x0a]	196721	1			T3	31		T6	34		T7	5
valid_sources[0x0b]	183156	1			T1	1		T3	4		T6	34
valid_sources[0x0c]	188613	1			T1	34		T6	39		T7	2
valid_sources[0x0d]	176441	1			T1	25		T3	46		T6	45
valid_sources[0x0e]	191731	1			T1	7		T6	48		T7	9
valid_sources[0x0f]	184506	1			T1	4		T3	12		T6	45
valid_sources[0x10]	179844	1			T1	5		T3	42		T6	41
valid_sources[0x11]	180881	1			T1	18		T3	5		T6	43
valid_sources[0x12]	182897	1			T6	34		T7	5		T8	484
valid_sources[0x13]	194307	1			T1	24		T3	6		T6	40
valid_sources[0x14]	174537	1			T1	14		T3	17		T6	47
valid_sources[0x15]	185154	1			T1	14		T6	52		T7	4
valid_sources[0x16]	183732	1			T3	5		T6	52		T7	4
valid_sources[0x17]	192014	1			T3	12		T6	59		T7	4
valid_sources[0x18]	181434	1			T1	14		T3	7		T5	102
valid_sources[0x19]	185866	1			T1	35		T3	26		T6	42
valid_sources[0x1a]	173420	1			T3	12		T6	46		T7	7
valid_sources[0x1b]	168967	1			T3	21		T6	56		T7	8
valid_sources[0x1c]	172767	1			T1	8		T3	21		T6	45
valid_sources[0x1d]	172384	1			T1	24		T3	74		T6	50
valid_sources[0x1e]	185580	1			T1	8		T3	2		T6	36
valid_sources[0x1f]	216777	1			T3	17		T6	23		T7	3
valid_sources[0x20]	174150	1			T1	8		T3	2		T6	40
valid_sources[0x21]	174465	1			T3	42		T6	41		T7	3
valid_sources[0x22]	183461	1			T1	3		T3	54		T6	51
valid_sources[0x23]	172912	1			T3	18		T6	49		T7	3
valid_sources[0x24]	188941	1			T1	2		T3	5		T6	45
valid_sources[0x25]	217213	1			T1	19		T3	6		T6	54
valid_sources[0x26]	194596	1			T3	6		T6	49		T7	5
valid_sources[0x27]	183222	1			T3	47		T6	43		T7	6
valid_sources[0x28]	179914	1			T1	7		T3	31		T6	45
valid_sources[0x29]	178733	1			T1	12		T6	55		T7	6
valid_sources[0x2a]	187868	1			T1	34		T3	2		T6	50
valid_sources[0x2b]	179096	1			T1	31		T6	52		T7	3
valid_sources[0x2c]	179447	1			T1	9		T3	15		T6	59
valid_sources[0x2d]	204484	1			T3	3		T6	37		T7	6
valid_sources[0x2e]	172066	1			T1	7		T3	24		T6	43
valid_sources[0x2f]	179371	1			T6	51		T7	5		T8	546
valid_sources[0x30]	180686	1			T1	9		T3	3		T6	35
valid_sources[0x31]	179152	1			T1	22		T3	23		T6	37
valid_sources[0x32]	164598	1			T1	11		T3	52		T6	45
valid_sources[0x33]	169818	1			T1	1		T3	74		T6	51
valid_sources[0x34]	177238	1			T1	30		T3	28		T6	44
valid_sources[0x35]	202220	1			T1	11		T3	11		T6	39
valid_sources[0x36]	181968	1			T1	33		T6	42		T7	4
valid_sources[0x37]	171065	1			T1	28		T3	19		T6	35
valid_sources[0x38]	175633	1			T1	5		T3	44		T6	37
valid_sources[0x39]	189718	1			T1	17		T3	1		T6	59
valid_sources[0x3a]	182331	1			T1	21		T6	50		T7	4
valid_sources[0x3b]	163759	1			T1	29		T3	10		T6	37
valid_sources[0x3c]	167232	1			T6	33		T7	4		T8	496
valid_sources[0x3d]	171591	1			T1	13		T3	39		T6	62
valid_sources[0x3e]	193272	1			T1	4		T3	36		T6	38
valid_sources[0x3f]	188142	1			T1	2		T6	42		T7	3
valid_sources[0x40]	175588	1			T1	2		T6	39		T7	9
valid_sources[0x41]	185798	1			T1	16		T3	24		T6	48
valid_sources[0x42]	186831	1			T1	28		T3	86		T6	43
valid_sources[0x43]	181775	1			T1	44		T6	38		T7	3
valid_sources[0x44]	190264	1			T1	15		T6	50		T7	8
valid_sources[0x45]	185285	1			T1	3		T3	25		T6	60
valid_sources[0x46]	187471	1			T1	4		T3	8		T6	43
valid_sources[0x47]	182325	1			T1	15		T3	18		T6	35
valid_sources[0x48]	174017	1			T3	82		T6	42		T7	7
valid_sources[0x49]	175143	1			T1	2		T6	62		T7	3
valid_sources[0x4a]	168487	1			T1	23		T6	47		T7	2
valid_sources[0x4b]	176242	1			T1	14		T3	1		T6	37
valid_sources[0x4c]	179626	1			T1	14		T3	31		T6	52
valid_sources[0x4d]	197922	1			T1	5		T6	48		T7	3
valid_sources[0x4e]	169286	1			T1	7		T6	42		T7	2
valid_sources[0x4f]	176069	1			T1	22		T6	37		T7	6
valid_sources[0x50]	184674	1			T1	5		T3	39		T6	42
valid_sources[0x51]	193801	1			T3	25		T6	46		T7	2
valid_sources[0x52]	205949	1			T1	8		T3	6		T6	43
valid_sources[0x53]	175016	1			T1	46		T3	24		T6	42
valid_sources[0x54]	181580	1			T1	3		T3	9		T6	44
valid_sources[0x55]	173961	1			T1	13		T3	3		T6	35
valid_sources[0x56]	187743	1			T1	25		T3	3		T6	46
valid_sources[0x57]	188424	1			T1	8		T3	6		T6	56
valid_sources[0x58]	192189	1			T1	15		T3	18		T6	63
valid_sources[0x59]	192927	1			T1	90		T3	60		T6	43
valid_sources[0x5a]	186416	1			T6	53		T7	5		T8	510
valid_sources[0x5b]	172570	1			T6	44		T7	6		T8	427
valid_sources[0x5c]	175184	1			T1	1		T3	11		T6	44
valid_sources[0x5d]	174856	1			T6	43		T7	8		T8	478
valid_sources[0x5e]	187773	1			T1	8		T3	15		T6	33
valid_sources[0x5f]	167421	1			T6	56		T7	2		T8	530
valid_sources[0x60]	189193	1			T1	16		T3	22		T6	42
valid_sources[0x61]	335735	1			T6	46		T7	6		T8	512
valid_sources[0x62]	177700	1			T1	18		T6	43		T8	500
valid_sources[0x63]	177975	1			T1	3		T3	13		T6	39
valid_sources[0x64]	175100	1			T1	18		T3	57		T6	45
valid_sources[0x65]	172867	1			T1	19		T3	14		T6	44
valid_sources[0x66]	215969	1			T3	2		T6	54		T7	5
valid_sources[0x67]	193250	1			T1	22		T6	40		T7	5
valid_sources[0x68]	211589	1			T1	30		T6	51		T7	4
valid_sources[0x69]	186262	1			T1	48		T3	23		T6	43
valid_sources[0x6a]	179231	1			T3	10		T6	52		T7	2
valid_sources[0x6b]	185708	1			T1	15		T3	28		T6	39
valid_sources[0x6c]	174336	1			T3	13		T6	43		T7	5
valid_sources[0x6d]	162464	1			T1	2		T6	55		T7	8
valid_sources[0x6e]	174712	1			T1	10		T6	49		T7	4
valid_sources[0x6f]	184171	1			T1	35		T6	54		T7	3
valid_sources[0x70]	195373	1			T3	38		T6	48		T7	3
valid_sources[0x71]	174124	1			T1	8		T3	19		T6	45
valid_sources[0x72]	181151	1			T1	1		T3	27		T6	35
valid_sources[0x73]	163746	1			T1	44		T6	48		T7	3
valid_sources[0x74]	186880	1			T1	2		T6	58		T7	4
valid_sources[0x75]	183201	1			T1	2		T6	47		T7	5
valid_sources[0x76]	178951	1			T1	16		T3	13		T6	40
valid_sources[0x77]	181797	1			T1	7		T3	23		T6	49
valid_sources[0x78]	175515	1			T1	29		T3	20		T6	57
valid_sources[0x79]	176594	1			T1	2		T3	16		T6	55
valid_sources[0x7a]	182440	1			T1	8		T3	12		T6	64
valid_sources[0x7b]	182977	1			T1	10		T3	8		T6	62
valid_sources[0x7c]	183186	1			T1	18		T6	46		T7	10
valid_sources[0x7d]	163228	1			T1	18		T6	47		T7	4
valid_sources[0x7e]	168971	1			T3	36		T6	40		T7	2
valid_sources[0x7f]	176112	1			T1	20		T6	55		T7	4
valid_sources[0x80]	179988	1			T1	31		T3	77		T6	45

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9639510

1

T1

921

T2

199

T3

1580

values[0x0]

all_enables

biggest_size

215842

1

T1

28

T2

73

T3

74

values[0x1]

all_enables

biggest_size

146757

1

T1

21

T2

51

T3

83