Unified Coverage Report :: Module :: i2c_bus_monitor

Module : i2c_bus_monitor

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.50	96.26	90.32		81.82	89.58

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_bus_monitor.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_bus_monitor	89.50	96.26	90.32		81.82	89.58

---

Module Instance : tb.dut.i2c_core.u_i2c_bus_monitor

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.50	96.26	90.32		81.82	89.58

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.50	96.26	90.32		81.82	89.58

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.58	97.74	79.23			93.33	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_bus_monitor

	Line No.	Total	Covered	Percent
TOTAL		107	103	96.26
CONT_ASSIGN	37	1	1	100.00
ALWAYS	40	3	3	100.00
ALWAYS	50	5	5	100.00
ALWAYS	82	6	6	100.00
ALWAYS	92	6	6	100.00
ALWAYS	102	6	6	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	3	3	100.00
ALWAYS	158	9	8	88.89
ALWAYS	189	46	45	97.83
ALWAYS	275	9	8	88.89
ALWAYS	293	3	2	66.67
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	304	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_bus_monitor.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_bus_monitor.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
37	1	1
40	1	1
41	1	1
43	1	1
50	1	1
51	1	1
52	1	1
54	1	1
55	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
87	1	1
			MISSING_ELSE
92	1	1
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
			MISSING_ELSE
102	1	1
103	1	1
104	1	1
105	1	1
106	1	1
107	1	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
117	1	1
118	1	1
119	1	1
127	1	1
137	1	1
147	1	1
148	1	1
150	1	1
158	1	1
159	1	1
160	1	1
163	1	1
166	0	1
			MISSING_ELSE
168	1	1
169	1	1
170	1	1
171	1	1
			MISSING_ELSE
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
196	1	1
198	1	1
200	1	1
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
223	0	1
			MISSING_ELSE
225	1	1
230	1	1
			MISSING_ELSE
235	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
251	1	1
252	1	1
253	1	1
			MISSING_ELSE
			MISSING_ELSE
259	1	1
261	1	1
262	1	1
263	1	1
264	1	1
			MISSING_ELSE
275	1	1
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
283	0	1
285	1	1
288	1	1
293	1	1
294	0	1
299	1	1
303	1	1
304	1	1

---

Cond Coverage for Module : i2c_bus_monitor

	Total	Covered	Percent
Conditions	93	84	90.32
Logical	93	84	90.32
Non-Logical	0	0
Event	0	0

 LINE       37
 EXPRESSION (controller_enable_i | target_enable_i | multi_controller_enable_i)
             ---------1---------   -------2-------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T2,T4,T5
1	0	0	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (start_det_trigger || stop_det_trigger)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (start_det_pending || stop_det_pending)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       96
 EXPRESSION (((!monitor_enable)) || ((!scl_i)) || start_det || stop_det_trigger)
             ---------1---------    -----2----    ----3----    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Covered	T1,T2,T3
1	0	0	0	Covered	T1,T2,T3

 LINE       106
 EXPRESSION (((!monitor_enable)) || ((!scl_i)) || stop_det || start_det_trigger)
             ---------1---------    -----2----    ----3---    --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Covered	T1,T2,T3
1	0	0	0	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (monitor_enable && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T79
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (monitor_enable && start_det_pending && (ctrl_det_count >= 14'(thd_dat_i)))
             -------1------    --------2--------    -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION (monitor_enable && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T80
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (monitor_enable && stop_det_pending && (ctrl_det_count >= 14'(thd_dat_i)))
             -------1------    --------2-------    -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T2,T3

 LINE       127
 EXPRESSION (scl_i && (sda_i == sda_i_q))
             --1--    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       127
 SUB-EXPRESSION (sda_i == sda_i_q)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (monitor_enable && ((!monitor_enable_q)))
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       170
 EXPRESSION (bus_release_cnt_dec && (bus_release_cnt != '0))
             ---------1---------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       170
 SUB-EXPRESSION (bus_release_cnt != '0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((!scl_i)) || ((!sda_i)))
             -----1----    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T50,T81

 LINE       214
 EXPRESSION (bus_idling && bus_inactive_timeout_en)
             -----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T3,T8
1	1	Covered	T2,T4,T5

 LINE       225
 EXPRESSION (bus_release_cnt == 30'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (bus_release_cnt == 30'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T50,T81

 LINE       261
 EXPRESSION (((!scl_i)) || ((!sda_i)))
             -----1----    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T53,T55,T82

 LINE       263
 EXPRESSION (bus_release_cnt == 30'b1)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       279
 EXPRESSION (monitor_enable && ((!monitor_enable_q)))
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       294
 EXPRESSION (state_q == StBusFree)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       299
 EXPRESSION (state_q != StBusBusyStop)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (bus_active_timeout_det_d && ((!bus_active_timeout_det_q)))
             ------------1-----------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       304
 EXPRESSION (((!target_idle_i)) && bus_inactive_timeout_det)
             ---------1--------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T50,T81

---

FSM Coverage for Module : i2c_bus_monitor

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	11	9	81.82
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StBusBusyHigh	283	Covered	T2,T4,T5
StBusBusyLow	201	Covered	T1,T2,T3
StBusBusyStop	211	Covered	T1,T2,T3
StBusFree	278	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StBusBusyHigh->StBusBusyLow	242	Covered	T2,T4,T5
StBusBusyHigh->StBusBusyStop	238	Covered	T53,T55
StBusBusyHigh->StBusFree	278	Covered	T2,T50,T81
StBusBusyLow->StBusBusyHigh	283	Covered	T2,T4,T5
StBusBusyLow->StBusBusyStop	211	Covered	T1,T2,T3
StBusBusyLow->StBusFree	278	Covered	T18,T19,T20
StBusBusyStop->StBusBusyHigh	283	Not Covered
StBusBusyStop->StBusBusyLow	262	Covered	T2,T4,T6
StBusBusyStop->StBusFree	278	Covered	T1,T2,T3
StBusFree->StBusBusyHigh	283	Not Covered
StBusFree->StBusBusyLow	201	Covered	T1,T2,T3

---

Branch Coverage for Module : i2c_bus_monitor

	Line No.	Total	Covered	Percent
Branches		48	43	89.58
IF	40	2	2	100.00
IF	50	2	2	100.00
IF	82	4	4	100.00
IF	92	4	4	100.00
IF	102	4	4	100.00
IF	147	2	2	100.00
IF	158	6	5	83.33
CASE	196	17	15	88.24
IF	275	5	4	80.00
IF	293	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_bus_monitor.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_bus_monitor.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	40	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	50	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	82	if ((!rst_ni))
-2-:	84	if ((start_det_trigger || stop_det_trigger))
-3-:	86	if ((start_det_pending || stop_det_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_ni))
-2-:	94	if (start_det_trigger)
-3-:	96	if (((((!monitor_enable) || (!scl_i)) || start_det) || stop_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	102	if ((!rst_ni))
-2-:	104	if (stop_det_trigger)
-3-:	106	if (((((!monitor_enable) || (!scl_i)) || stop_det) || start_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	147	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	158	if ((!rst_ni))
-2-:	160	if ((monitor_enable && (!monitor_enable_q)))
-3-:	163	if (multi_controller_enable_i)
-4-:	168	if (bus_release_cnt_load)
-5-:	170	if ((bus_release_cnt_dec && (bus_release_cnt != '0)))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	Not Covered
0	1	0	-	-	Covered	T1,T2,T3
0	0	-	1	-	Covered	T1,T2,T3
0	0	-	0	1	Covered	T1,T2,T3
0	0	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	196	case (state_q)
-2-:	200	if (((!scl_i) || (!sda_i)))
-3-:	210	if (stop_det)
-4-:	214	if ((bus_idling && bus_inactive_timeout_en))
-5-:	218	if (scl_i)
-6-:	221	if (bus_active_timeout_det_q)
-7-:	225	if ((bus_release_cnt == 30'b1))
-8-:	237	if (stop_det)
-9-:	241	if ((!bus_idling))
-10-:	245	if ((bus_release_cnt == 30'b1))
-11-:	252	if (sda_i)
-12-:	261	if (((!scl_i) || (!sda_i)))
-13-:	263	if ((bus_release_cnt == 30'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StBusFree	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StBusFree	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StBusBusyLow	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StBusBusyLow	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
StBusBusyLow	-	0	0	1	1	-	-	-	-	-	-	-	Not Covered
StBusBusyLow	-	0	0	1	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
StBusBusyLow	-	0	0	0	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
StBusBusyLow	-	0	0	0	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
StBusBusyHigh	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T53,T55
StBusBusyHigh	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T2,T4,T5
StBusBusyHigh	-	-	-	-	-	-	0	0	1	1	-	-	Covered	T2,T50,T81
StBusBusyHigh	-	-	-	-	-	-	0	0	1	0	-	-	Covered	T2,T50,T81
StBusBusyHigh	-	-	-	-	-	-	0	0	0	-	-	-	Covered	T2,T4,T5
StBusBusyStop	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T4,T6
StBusBusyStop	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T3
StBusBusyStop	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	275	if ((!rst_ni))
-2-:	277	if ((!monitor_enable))
-3-:	279	if ((monitor_enable && (!monitor_enable_q)))
-4-:	280	if (multi_controller_enable_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if (multi_controller_enable_i)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3