Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	385961390	0	0	0
ctrl_rd_A	385961390	2313	0	0
host_fifo_config_rd_A	385961390	3894	0	0
host_nack_handler_timeout_rd_A	385961390	1394	0	0
host_timeout_ctrl_rd_A	385961390	1145	0	0
intr_enable_rd_A	385961390	3610	0	0
ovrd_rd_A	385961390	2103	0	0
target_fifo_config_rd_A	385961390	1507	0	0
target_id_rd_A	385961390	1768	0	0
target_timeout_ctrl_rd_A	385961390	1457	0	0
timeout_ctrl_rd_A	385961390	1510	0	0
timing0_rd_A	385961390	1456	0	0
timing1_rd_A	385961390	1449	0	0
timing2_rd_A	385961390	1265	0	0
timing3_rd_A	385961390	1463	0	0
timing4_rd_A	385961390	1308	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	2313	0	0
T105	13726	312	0	0
T106	7243	156	0	0
T107	3775	88	0	0
T108	3622	14	0	0
T109	2409	28	0	0
T110	1401	1	0	0
T111	23310	154	0	0
T112	2033	30	0	0
T113	16161	225	0	0
T114	9362	36	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	3894	0	0
T13	7648	0	0	0
T72	53466	0	0	0
T115	280368	111	0	0
T116	0	209	0	0
T117	0	120	0	0
T118	0	154	0	0
T119	0	121	0	0
T120	0	207	0	0
T121	0	103	0	0
T122	0	122	0	0
T123	0	146	0	0
T124	0	74	0	0
T125	8011	0	0	0
T126	15316	0	0	0
T127	39598	0	0	0
T128	994	0	0	0
T129	318022	0	0	0
T130	14659	0	0	0
T131	46050	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1394	0	0
T105	13726	101	0	0
T106	7243	55	0	0
T107	3775	17	0	0
T108	3622	35	0	0
T109	2409	13	0	0
T111	23310	123	0	0
T112	2033	5	0	0
T113	16161	131	0	0
T114	9362	21	0	0
T132	5609	115	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1145	0	0
T105	13726	59	0	0
T106	7243	43	0	0
T107	3775	20	0	0
T108	3622	34	0	0
T109	2409	5	0	0
T110	1401	8	0	0
T111	23310	127	0	0
T112	2033	10	0	0
T113	16161	68	0	0
T114	9362	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	3610	0	0
T105	13726	574	0	0
T106	7243	189	0	0
T107	3775	76	0	0
T108	3622	29	0	0
T109	2409	51	0	0
T111	23310	139	0	0
T133	1831	4	0	0
T134	982	11	0	0
T135	1623	7	0	0
T136	1287	24	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	2103	0	0
T82	2060	36	0	0
T137	0	52	0	0
T138	0	60	0	0
T139	0	24	0	0
T140	0	36	0	0
T141	0	52	0	0
T142	0	33	0	0
T143	0	15	0	0
T144	0	64	0	0
T145	0	68	0	0
T146	11047	0	0	0
T147	58390	0	0	0
T148	883	0	0	0
T149	66000	0	0	0
T150	5569	0	0	0
T151	126696	0	0	0
T152	128792	0	0	0
T153	16292	0	0	0
T154	171535	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1507	0	0
T105	13726	91	0	0
T106	7243	68	0	0
T107	3775	16	0	0
T108	3622	42	0	0
T109	2409	4	0	0
T110	1401	8	0	0
T111	23310	110	0	0
T112	2033	6	0	0
T113	16161	127	0	0
T114	9362	29	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1768	0	0
T105	13726	248	0	0
T106	7243	124	0	0
T107	3775	26	0	0
T108	3622	39	0	0
T109	2409	11	0	0
T110	1401	10	0	0
T111	23310	124	0	0
T112	2033	24	0	0
T113	16161	125	0	0
T114	9362	13	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1457	0	0
T105	13726	121	0	0
T106	7243	35	0	0
T107	3775	32	0	0
T108	3622	39	0	0
T109	2409	2	0	0
T110	1401	13	0	0
T111	23310	163	0	0
T112	2033	10	0	0
T113	16161	117	0	0
T114	9362	24	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1510	0	0
T105	13726	131	0	0
T106	7243	70	0	0
T107	3775	18	0	0
T108	3622	3	0	0
T109	2409	14	0	0
T110	1401	6	0	0
T111	23310	100	0	0
T112	2033	15	0	0
T113	16161	137	0	0
T114	9362	41	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1456	0	0
T105	13726	141	0	0
T106	7243	46	0	0
T107	3775	13	0	0
T108	3622	38	0	0
T109	2409	9	0	0
T110	1401	10	0	0
T111	23310	149	0	0
T112	2033	10	0	0
T113	16161	118	0	0
T114	9362	26	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1449	0	0
T105	13726	138	0	0
T106	7243	54	0	0
T107	3775	16	0	0
T108	3622	5	0	0
T109	2409	15	0	0
T110	1401	11	0	0
T111	23310	163	0	0
T112	2033	16	0	0
T113	16161	95	0	0
T114	9362	38	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1265	0	0
T105	13726	100	0	0
T106	7243	30	0	0
T107	3775	16	0	0
T108	3622	2	0	0
T109	2409	17	0	0
T110	1401	4	0	0
T111	23310	142	0	0
T112	2033	4	0	0
T113	16161	119	0	0
T114	9362	15	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1463	0	0
T105	13726	134	0	0
T106	7243	71	0	0
T107	3775	17	0	0
T108	3622	43	0	0
T109	2409	15	0	0
T110	1401	1	0	0
T111	23310	125	0	0
T112	2033	15	0	0
T113	16161	94	0	0
T114	9362	41	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385961390	1308	0	0
T105	13726	123	0	0
T106	7243	42	0	0
T107	3775	17	0	0
T108	3622	14	0	0
T109	2409	10	0	0
T110	1401	6	0	0
T111	23310	157	0	0
T112	2033	6	0	0
T113	16161	101	0	0
T114	9362	12	0	0