Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
89.57 89.57 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_protocol_cov_cg 89.57 1 100 1 64 64



Group Instance : i2c_protocol_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
89.57 1 100 1 64 64



Summary for Group Instance i2c_protocol_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 47 7 40 85.11
Crosses 68 5 63 92.65


Variables for Group Instance i2c_protocol_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
RStart_before_read_data_ACK_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_Ack_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_transmission_cp 1 1 0 0.00 100 1 1 0
RStart_during_read_data_cp 1 0 1 100.00 100 1 1 0
RStart_during_rw_bit_cp 1 1 0 0.00 100 1 1 0
RStart_during_write_data_cp 1 0 1 100.00 100 1 1 0
Read_data_ack_before_stop_cp 1 1 0 0.00 100 1 1 0
Rstart_after_Address_Ack_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Nack_cp 1 0 1 100.00 100 1 1 0
Start_followed_by_Rstart_cp 1 0 1 100.00 100 1 1 2
Stop_after_read_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_read_data_ack_cp 1 1 0 0.00 100 1 1 0
Stop_after_write_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_write_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_addr_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_data_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_read_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_write_cp 1 1 0 0.00 100 1 1 0
bus_state_cp 17 0 17 100.00 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0
num_rd_bytes_cp 5 0 5 100.00 100 1 1 0
num_wr_bytes_cp 5 0 5 100.00 100 1 1 0


Crosses for Group Instance i2c_protocol_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
bus_state_x_ip_mode_cp 34 1 33 97.06 100 1 1 0
num_rd_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
num_wr_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
Stop_after_write_data_ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Stop_after_read_data_ack_x_ip_mode_cp 2 2 0 0.00 100 1 1 0
Stop_after_write_data_Nack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Stop_after_read_data_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Start_followed_by_Rstart_cp_x_ip_mode_cp 2 1 1 50.00 100 1 1 0


Summary for Variable RStart_before_read_data_ACK_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_before_read_data_ACK_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_before_read_data_ACK_Nack 12856 1 T3 5 T8 13 T38 108


Summary for Variable RStart_during_address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_address_Acknowledge 8 1 T48 4 T49 4


Summary for Variable RStart_during_address_transmission_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for RStart_during_address_transmission_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Start_during_address_transmission 0 1 1


Summary for Variable RStart_during_read_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_read_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_read_data 24 1 T48 12 T49 12


Summary for Variable RStart_during_rw_bit_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for RStart_during_rw_bit_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Start_during_rw_bit 0 1 1


Summary for Variable RStart_during_write_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_write_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_write_data 21483 1 T50 17 T45 29 T46 64


Summary for Variable Read_data_ack_before_stop_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Read_data_ack_before_stop_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Read_data_ack_before_stop 0 1 1


Summary for Variable Rstart_after_Address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack 26 1 T11 1 T12 1 T48 10


Summary for Variable Rstart_after_Address_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack 72 1 T19 1 T21 1 T258 1


Summary for Variable Start_followed_by_Rstart_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for Start_followed_by_Rstart_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[1] 162 1 T14 159 T267 3


Summary for Variable Stop_after_read_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack 10782 1 T2 1 T4 18 T7 2


Summary for Variable Stop_after_read_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_after_read_data_ack_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_after_read_data_ack 0 1 1


Summary for Variable Stop_after_write_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack 46 1 T14 1 T19 4 T20 1


Summary for Variable Stop_after_write_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack 8991 1 T1 16 T2 1 T4 19


Summary for Variable Stop_without_ACK_after_addr_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_addr_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_addr 0 1 1


Summary for Variable Stop_without_ACK_after_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_data 5945 1 T45 7 T46 2 T47 3


Summary for Variable Stop_without_ACK_after_read_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_read_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_read 0 1 1


Summary for Variable Stop_without_ACK_after_write_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_write_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_write 0 1 1


Summary for Variable bus_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 17 0 17 100.00


User Defined Bins for bus_state_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle 265091 1 T1 1 T2 1 T3 1
stop 21454 1 T1 16 T2 2 T4 37
write_data_nack 25630 1 T50 4 T51 4 T52 4
write_data_ack 1402576 1 T1 451 T2 186 T4 4311
read_data_nack 88510 1 T2 8 T3 19 T4 76
read_data_ack 1127303 1 T3 138 T4 4195 T7 81
write_data 9668774 1 T1 2693 T2 1136 T4 25594
read_data 7880722 1 T2 46 T3 952 T4 29720
write_addr_nack 31450 1 T19 285 T57 4 T20 52
write_addr_ack 107183 1 T1 55 T2 11 T4 70
read_addr_nack 66358 1 T19 60 T20 3912 T21 842
read_addr_ack 85595 1 T2 8 T3 20 T4 64
write 128428 1 T1 68 T2 12 T4 76
read 73867 1 T2 6 T3 18 T4 57
addr 1189442 1 T1 300 T2 91 T3 116
rstart 89577 1 T2 4 T3 12 T5 20
start 56265 1 T1 44 T2 7 T3 2


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 12702803 1 T3 1278 T8 1810 T38 19780
host 9605422 1 T1 3628 T2 1518 T4 64972


Summary for Variable num_rd_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_rd_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 32547 1 T4 76 T25 64 T38 29
high 1191335 1 T4 10609 T25 8934 T38 1280
mid 1881087 1 T4 11692 T7 59 T28 1141
low 4520949 1 T3 883 T4 10644 T7 550
one 494080 1 T2 8 T3 108 T4 512


Summary for Variable num_wr_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_wr_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 38664 1 T4 95 T5 438 T25 80
high 1209773 1 T4 9338 T5 8786 T25 7862
mid 1906687 1 T1 502 T2 228 T4 10268
low 5032470 1 T1 1951 T2 955 T4 9326
one 625818 1 T1 338 T2 78 T4 470


Summary for Cross bus_state_x_ip_mode_cp

Samples crossed: bus_state_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 34 1 33 97.06 1


Automatically Generated Cross Bins for bus_state_x_ip_mode_cp

Uncovered bins
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[read_addr_nack] [device] 0 1 1


Covered bins
bus_state_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle device 262209 1 T3 1 T8 1 T38 1
idle host 2882 1 T1 1 T2 1 T4 1
stop device 12071 1 T38 4 T45 12 T46 2
stop host 9383 1 T1 16 T2 2 T4 37
write_data_nack device 392 1 T50 4 T51 4 T52 4
write_data_nack host 25238 1 T14 650 T27 30 T19 326
write_data_ack device 837967 1 T50 860 T45 735 T46 1403
write_data_ack host 564609 1 T1 451 T2 186 T4 4311
read_data_nack device 63108 1 T3 19 T8 43 T38 344
read_data_nack host 25402 1 T2 8 T4 76 T7 8
read_data_ack device 489070 1 T3 138 T8 148 T38 1942
read_data_ack host 638233 1 T4 4195 T7 81 T29 4
write_data device 6283597 1 T50 6196 T45 6105 T46 11833
write_data host 3385177 1 T1 2693 T2 1136 T4 25594
read_data device 3288001 1 T3 952 T8 1227 T38 13978
read_data host 4592721 1 T2 46 T4 29720 T6 2
write_addr_nack device 28 1 T57 4 T58 4 T48 4
write_addr_nack host 31422 1 T19 285 T20 52 T21 361
write_addr_ack device 93510 1 T50 63 T45 103 T46 201
write_addr_ack host 13673 1 T1 55 T2 11 T4 70
read_addr_nack host 66358 1 T19 60 T20 3912 T21 842
read_addr_ack device 66568 1 T3 20 T8 51 T38 395
read_addr_ack host 19027 1 T2 8 T4 64 T6 6
write device 111947 1 T50 72 T45 144 T46 268
write host 16481 1 T1 68 T2 12 T4 76
read device 57069 1 T3 18 T8 42 T38 339
read host 16798 1 T2 6 T4 57 T6 9
addr device 1017179 1 T3 116 T8 258 T38 2527
addr host 172263 1 T1 300 T2 91 T4 672
rstart device 87866 1 T3 12 T8 37 T38 238
rstart host 1711 1 T2 4 T5 20 T7 3
start device 32221 1 T3 2 T8 3 T38 12
start host 24044 1 T1 44 T2 7 T4 99


Summary for Cross num_rd_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_rd_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_rd_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 1509 1 T38 29 T67 48 T175 24
device high 87293 1 T38 1280 T39 75 T67 992
device mid 377483 1 T38 2647 T45 3 T39 904
device low 2547026 1 T3 883 T8 777 T38 7876
device one 354351 1 T3 108 T8 342 T38 1235
host sixtyfour 31038 1 T4 76 T25 64 T75 320
host high 1104042 1 T4 10609 T25 8934 T75 6712
host mid 1503604 1 T4 11692 T7 59 T28 1141
host low 1973923 1 T4 10644 T7 550 T29 4
host one 139729 1 T2 8 T4 512 T7 34


Summary for Cross num_wr_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_wr_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_wr_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 10872 1 T50 26 T46 26 T47 28
device high 315689 1 T50 552 T45 193 T46 660
device mid 861369 1 T50 1531 T45 626 T46 2260
device low 3866257 1 T50 2380 T45 4403 T46 6605
device one 530674 1 T50 308 T45 733 T46 750
host sixtyfour 27792 1 T4 95 T5 438 T25 80
host high 894084 1 T4 9338 T5 8786 T25 7862
host mid 1045318 1 T1 502 T2 228 T4 10268
host low 1166213 1 T1 1951 T2 955 T4 9326
host one 95144 1 T1 338 T2 78 T4 470


Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp

Bins
Stop_after_write_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack device 5923 1 T45 7 T46 2 T47 3
Stop_after_write_data_ack host 3068 1 T1 16 T2 1 T4 19


Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 2 0 0.00 2


Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp

Uncovered bins
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* * -- -- 2


Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp

Element holes
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Covered bins
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack host 46 1 T14 1 T19 4 T20 1


Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp

Bins
Stop_after_read_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack device 5765 1 T38 4 T45 5 T39 11
Stop_after_read_data_Nack host 5017 1 T2 1 T4 18 T7 2


Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp

Bins
Rstart_after_Address_Ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack device 20 1 T48 10 T49 10 - -
Rstart_after_Address_Ack host 6 1 T11 1 T12 1 T268 1


Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp

Bins
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack device 8 1 T48 4 T49 4 - -
Rstart_after_Address_Nack host 64 1 T19 1 T21 1 T258 1


Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp

Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp

Element holes
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Excluded/Illegal bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTSTATUS
[auto[0]] [device , host] -- Excluded (2 bins)


Covered bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[1] host 162 1 T14 159 T267 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%