Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25363613	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7120063

1

T1

1435

T2

1859

T3

37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31705769	1			T1	2605		T2	7376		T3	28
values[0x0]	388201	1			T1	133		T2	65		T3	42
values[0x1]	389706	1			T1	145		T2	58		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17728810	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14754866

1

T1

1747

T2

3453

T3

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	121585	1			T3	1		T4	163		T5	6
valid_sources[0x01]	118124	1			T3	1		T4	166		T5	11
valid_sources[0x02]	116816	1			T2	1		T3	1		T4	193
valid_sources[0x03]	123238	1			T2	1		T4	177		T5	6
valid_sources[0x04]	111021	1			T4	202		T5	11		T6	2
valid_sources[0x05]	120772	1			T2	507		T4	180		T5	10
valid_sources[0x06]	126829	1			T4	197		T5	6		T6	6
valid_sources[0x07]	126181	1			T2	3		T3	1		T4	194
valid_sources[0x08]	133495	1			T4	185		T5	5		T6	6
valid_sources[0x09]	120426	1			T2	1		T4	188		T5	11
valid_sources[0x0a]	132902	1			T2	1		T4	180		T5	14
valid_sources[0x0b]	117771	1			T2	1		T4	185		T5	8
valid_sources[0x0c]	126944	1			T4	182		T5	101		T6	5
valid_sources[0x0d]	133343	1			T4	180		T5	623		T6	3
valid_sources[0x0e]	112415	1			T4	199		T5	11		T6	4
valid_sources[0x0f]	134168	1			T4	164		T5	21		T6	3
valid_sources[0x10]	120559	1			T4	182		T5	14		T6	2
valid_sources[0x11]	132178	1			T3	2		T4	175		T5	20
valid_sources[0x12]	132862	1			T2	1020		T4	191		T5	317
valid_sources[0x13]	120776	1			T2	1		T3	1		T4	191
valid_sources[0x14]	110669	1			T4	197		T5	5		T6	3
valid_sources[0x15]	129332	1			T2	1		T3	1		T4	171
valid_sources[0x16]	126733	1			T4	189		T5	308		T6	2
valid_sources[0x17]	120619	1			T2	1		T4	197		T5	106
valid_sources[0x18]	124449	1			T4	179		T5	102		T6	3
valid_sources[0x19]	114356	1			T2	1		T4	192		T5	5
valid_sources[0x1a]	117621	1			T4	203		T5	208		T6	4
valid_sources[0x1b]	114297	1			T2	1		T4	198		T5	6
valid_sources[0x1c]	125318	1			T4	189		T5	7		T6	2
valid_sources[0x1d]	121354	1			T4	181		T5	519		T6	5
valid_sources[0x1e]	115342	1			T3	2		T4	187		T5	15
valid_sources[0x1f]	135264	1			T3	4		T4	191		T5	9
valid_sources[0x20]	117262	1			T4	178		T5	4		T6	6
valid_sources[0x21]	117430	1			T4	212		T5	5		T6	1
valid_sources[0x22]	116268	1			T4	195		T5	22		T6	3
valid_sources[0x23]	118394	1			T4	204		T5	4		T6	5
valid_sources[0x24]	130394	1			T3	1		T4	179		T5	8
valid_sources[0x25]	128802	1			T3	2		T4	182		T5	16
valid_sources[0x26]	116099	1			T2	1		T4	199		T5	11
valid_sources[0x27]	123233	1			T2	1		T4	186		T5	9
valid_sources[0x28]	155656	1			T4	211		T5	1398		T6	2
valid_sources[0x29]	125600	1			T4	192		T5	308		T6	3
valid_sources[0x2a]	120237	1			T3	1		T4	175		T5	12
valid_sources[0x2b]	130776	1			T4	177		T5	15		T6	5
valid_sources[0x2c]	118051	1			T3	1		T4	203		T5	8
valid_sources[0x2d]	125483	1			T4	207		T5	303		T6	6
valid_sources[0x2e]	123298	1			T4	187		T5	16		T6	1
valid_sources[0x2f]	130279	1			T4	201		T5	106		T6	4
valid_sources[0x30]	124288	1			T4	183		T5	516		T6	3
valid_sources[0x31]	138320	1			T4	185		T5	12		T7	12
valid_sources[0x32]	143802	1			T4	177		T5	7		T6	2
valid_sources[0x33]	123676	1			T4	198		T5	13		T6	3
valid_sources[0x34]	136763	1			T3	1		T4	178		T5	8
valid_sources[0x35]	128091	1			T4	194		T5	8		T6	4
valid_sources[0x36]	128953	1			T3	2		T4	175		T5	396
valid_sources[0x37]	116800	1			T4	177		T5	6		T6	7
valid_sources[0x38]	131966	1			T4	178		T5	97		T6	1
valid_sources[0x39]	136817	1			T4	195		T5	7		T6	2
valid_sources[0x3a]	115889	1			T4	170		T5	116		T6	2
valid_sources[0x3b]	113731	1			T4	194		T5	4		T6	3
valid_sources[0x3c]	130529	1			T3	1		T4	204		T5	8
valid_sources[0x3d]	129495	1			T2	1		T3	1		T4	180
valid_sources[0x3e]	121858	1			T4	183		T5	9		T6	4
valid_sources[0x3f]	134802	1			T2	515		T3	1		T4	202
valid_sources[0x40]	121031	1			T2	1		T4	169		T5	14
valid_sources[0x41]	124583	1			T4	189		T5	16		T6	4
valid_sources[0x42]	116894	1			T4	194		T5	17		T6	5
valid_sources[0x43]	110856	1			T3	2		T4	199		T5	500
valid_sources[0x44]	120165	1			T4	178		T5	3		T6	3
valid_sources[0x45]	116127	1			T4	207		T5	11		T6	5
valid_sources[0x46]	120363	1			T4	212		T5	11		T6	1
valid_sources[0x47]	126373	1			T4	161		T5	9		T6	5
valid_sources[0x48]	129547	1			T4	179		T5	7		T6	5
valid_sources[0x49]	117826	1			T4	199		T5	6		T6	1
valid_sources[0x4a]	118026	1			T3	1		T4	196		T5	7
valid_sources[0x4b]	123804	1			T2	1		T4	205		T5	10
valid_sources[0x4c]	121677	1			T4	198		T5	402		T6	4
valid_sources[0x4d]	126943	1			T4	204		T5	695		T6	5
valid_sources[0x4e]	135112	1			T4	193		T5	9		T6	3
valid_sources[0x4f]	123561	1			T2	1		T4	172		T5	676
valid_sources[0x50]	140146	1			T3	1		T4	213		T5	19
valid_sources[0x51]	127158	1			T4	178		T5	4		T6	1
valid_sources[0x52]	140213	1			T2	1		T3	1		T4	180
valid_sources[0x53]	117064	1			T4	164		T5	6		T6	3
valid_sources[0x54]	126102	1			T2	505		T3	1		T4	195
valid_sources[0x55]	119988	1			T4	184		T5	21		T6	1
valid_sources[0x56]	183610	1			T3	1		T4	187		T5	681
valid_sources[0x57]	137219	1			T2	2		T4	197		T5	412
valid_sources[0x58]	128514	1			T2	1		T4	200		T5	791
valid_sources[0x59]	129451	1			T4	180		T5	5		T6	2
valid_sources[0x5a]	133823	1			T4	216		T5	314		T6	1
valid_sources[0x5b]	119984	1			T4	191		T5	6		T7	17
valid_sources[0x5c]	127633	1			T4	188		T5	121		T6	4
valid_sources[0x5d]	126577	1			T4	187		T5	210		T6	3
valid_sources[0x5e]	120043	1			T2	1		T4	196		T5	12
valid_sources[0x5f]	132137	1			T4	185		T5	18		T6	8
valid_sources[0x60]	131271	1			T3	1		T4	197		T5	10
valid_sources[0x61]	114775	1			T2	1		T3	1		T4	234
valid_sources[0x62]	113793	1			T4	183		T5	14		T6	2
valid_sources[0x63]	128765	1			T4	220		T5	109		T6	4
valid_sources[0x64]	115132	1			T4	189		T5	676		T6	3
valid_sources[0x65]	117604	1			T2	1		T3	4		T4	180
valid_sources[0x66]	123659	1			T3	2		T4	176		T5	8
valid_sources[0x67]	123193	1			T1	2883		T4	197		T5	5
valid_sources[0x68]	114207	1			T2	2		T3	1		T4	193
valid_sources[0x69]	122208	1			T2	1		T4	191		T5	19
valid_sources[0x6a]	120205	1			T4	196		T5	12		T6	2
valid_sources[0x6b]	124269	1			T4	202		T5	8		T6	1
valid_sources[0x6c]	156089	1			T4	222		T5	219		T6	3
valid_sources[0x6d]	148283	1			T3	1		T4	171		T5	110
valid_sources[0x6e]	123548	1			T2	1		T4	189		T5	29
valid_sources[0x6f]	151918	1			T4	165		T5	8		T6	6
valid_sources[0x70]	142349	1			T4	180		T5	215		T6	3
valid_sources[0x71]	137288	1			T2	1		T4	186		T5	194
valid_sources[0x72]	135010	1			T4	189		T5	6		T6	2
valid_sources[0x73]	134925	1			T2	1		T4	177		T5	10
valid_sources[0x74]	133814	1			T3	3		T4	191		T5	125
valid_sources[0x75]	117834	1			T4	192		T5	4		T6	2
valid_sources[0x76]	129356	1			T2	2		T4	199		T5	116
valid_sources[0x77]	117758	1			T2	511		T3	1		T4	189
valid_sources[0x78]	148684	1			T4	194		T5	106		T6	2
valid_sources[0x79]	129245	1			T4	186		T5	5		T6	2
valid_sources[0x7a]	123355	1			T2	1		T4	183		T5	11
valid_sources[0x7b]	132370	1			T2	1		T4	196		T5	211
valid_sources[0x7c]	119960	1			T3	1		T4	185		T5	17
valid_sources[0x7d]	127174	1			T3	1		T4	182		T5	695
valid_sources[0x7e]	138239	1			T3	3		T4	173		T5	12
valid_sources[0x7f]	118820	1			T2	443		T3	3		T4	196
valid_sources[0x80]	136786	1			T3	2		T4	179		T5	712

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6775260

1

T1

1225

T2

1799

T3

3

values[0x0]

all_enables

biggest_size

204213

1

T1

101

T2

35

T3

22

values[0x1]

all_enables

biggest_size

140590

1

T1

109

T2

25

T3

12