Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	396949832	0	0	0
ctrl_rd_A	396949832	1955	0	0
host_fifo_config_rd_A	396949832	3968	0	0
host_nack_handler_timeout_rd_A	396949832	1334	0	0
host_timeout_ctrl_rd_A	396949832	1185	0	0
intr_enable_rd_A	396949832	3390	0	0
ovrd_rd_A	396949832	2360	0	0
target_fifo_config_rd_A	396949832	1483	0	0
target_id_rd_A	396949832	1563	0	0
target_timeout_ctrl_rd_A	396949832	1338	0	0
timeout_ctrl_rd_A	396949832	1444	0	0
timing0_rd_A	396949832	1336	0	0
timing1_rd_A	396949832	1314	0	0
timing2_rd_A	396949832	1372	0	0
timing3_rd_A	396949832	1366	0	0
timing4_rd_A	396949832	1196	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1955	0	0
T96	2720	33	0	0
T97	6461	70	0	0
T98	6342	47	0	0
T99	13512	328	0	0
T100	7005	113	0	0
T101	4112	14	0	0
T102	8078	124	0	0
T103	2792	2	0	0
T104	5837	80	0	0
T105	7593	105	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	3968	0	0
T4	500329	276	0	0
T5	365604	0	0	0
T6	15007	0	0	0
T7	40381	0	0	0
T8	13373	0	0	0
T9	27287	0	0	0
T10	1103	0	0	0
T14	0	134	0	0
T17	9807	0	0	0
T25	0	182	0	0
T28	93167	0	0	0
T29	8446	0	0	0
T106	0	145	0	0
T107	0	114	0	0
T108	0	158	0	0
T109	0	156	0	0
T110	0	169	0	0
T111	0	162	0	0
T112	0	194	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1334	0	0
T96	2720	1	0	0
T97	6461	6	0	0
T98	6342	17	0	0
T99	13512	129	0	0
T100	7005	53	0	0
T101	4112	45	0	0
T102	8078	63	0	0
T103	2792	10	0	0
T104	5837	58	0	0
T105	7593	42	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1185	0	0
T96	2720	9	0	0
T97	6461	34	0	0
T98	6342	30	0	0
T99	13512	69	0	0
T100	7005	42	0	0
T101	4112	18	0	0
T102	8078	54	0	0
T103	2792	16	0	0
T104	5837	44	0	0
T105	7593	37	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	3390	0	0
T23	417398	25	0	0
T96	0	129	0	0
T97	0	22	0	0
T113	0	21	0	0
T114	0	10	0	0
T115	0	10	0	0
T116	0	20	0	0
T117	0	14	0	0
T118	0	15	0	0
T119	0	13	0	0
T120	108121	0	0	0
T121	102410	0	0	0
T122	19058	0	0	0
T123	29376	0	0	0
T124	264804	0	0	0
T125	213403	0	0	0
T126	37426	0	0	0
T127	192243	0	0	0
T128	38011	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	2360	0	0
T42	12179	0	0	0
T65	57426	0	0	0
T74	126017	0	0	0
T90	2693	55	0	0
T129	0	40	0	0
T130	0	73	0	0
T131	0	68	0	0
T132	0	58	0	0
T133	0	39	0	0
T134	0	74	0	0
T135	0	38	0	0
T136	0	32	0	0
T137	0	53	0	0
T138	114167	0	0	0
T139	14529	0	0	0
T140	2034	0	0	0
T141	39684	0	0	0
T142	98544	0	0	0
T143	30844	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1483	0	0
T96	2720	6	0	0
T97	6461	86	0	0
T98	6342	85	0	0
T99	13512	82	0	0
T100	7005	63	0	0
T101	4112	64	0	0
T102	8078	58	0	0
T103	2792	4	0	0
T104	5837	44	0	0
T105	7593	72	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1563	0	0
T96	2720	26	0	0
T97	6461	37	0	0
T98	6342	52	0	0
T99	13512	145	0	0
T100	7005	66	0	0
T101	4112	37	0	0
T102	8078	77	0	0
T103	2792	12	0	0
T104	5837	96	0	0
T105	7593	68	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1338	0	0
T96	2720	18	0	0
T97	6461	49	0	0
T98	6342	58	0	0
T99	13512	102	0	0
T100	7005	46	0	0
T101	4112	52	0	0
T102	8078	55	0	0
T103	2792	8	0	0
T104	5837	62	0	0
T105	7593	60	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1444	0	0
T96	2720	19	0	0
T97	6461	67	0	0
T98	6342	35	0	0
T99	13512	151	0	0
T100	7005	84	0	0
T101	4112	31	0	0
T102	8078	64	0	0
T103	2792	2	0	0
T104	5837	42	0	0
T105	7593	61	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1336	0	0
T96	2720	9	0	0
T97	6461	53	0	0
T98	6342	69	0	0
T99	13512	100	0	0
T100	7005	46	0	0
T101	4112	16	0	0
T102	8078	47	0	0
T103	2792	4	0	0
T104	5837	47	0	0
T105	7593	61	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1314	0	0
T96	2720	10	0	0
T97	6461	73	0	0
T98	6342	60	0	0
T99	13512	120	0	0
T100	7005	68	0	0
T101	4112	57	0	0
T102	8078	64	0	0
T103	2792	11	0	0
T104	5837	59	0	0
T105	7593	51	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1372	0	0
T96	2720	4	0	0
T97	6461	63	0	0
T98	6342	74	0	0
T99	13512	160	0	0
T100	7005	55	0	0
T101	4112	21	0	0
T102	8078	66	0	0
T104	5837	38	0	0
T105	7593	68	0	0
T144	2753	10	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1366	0	0
T96	2720	10	0	0
T97	6461	51	0	0
T98	6342	38	0	0
T99	13512	68	0	0
T100	7005	56	0	0
T101	4112	50	0	0
T102	8078	29	0	0
T103	2792	10	0	0
T104	5837	44	0	0
T105	7593	61	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396949832	1196	0	0
T96	2720	19	0	0
T97	6461	36	0	0
T98	6342	53	0	0
T99	13512	114	0	0
T100	7005	42	0	0
T101	4112	10	0	0
T102	8078	43	0	0
T103	2792	8	0	0
T104	5837	38	0	0
T105	7593	46	0	0