Unified Coverage Report :: Group :: i2c_env_pkg::i2c_scl_sda_override_cg

Group : i2c_env_pkg::i2c_scl_sda_override_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.scl_sda_override_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.scl_sda_override_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.scl_sda_override_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.scl_sda_override_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_sclval	2	0	2	100.00	100	1	1	2
cp_sdaval	2	0	2	100.00	100	1	1	2
cp_txorvden	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.scl_sda_override_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_txorvden_x_sclval	4	0	4	100.00	100	1	1	0
cp_txorvden_x_sdaval	4	0	4	100.00	100	1	1	0

Summary for Variable cp_sclval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sclval

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

358

1

T96

5

T97

8

T98

14

auto[1]

379

1

T96

7

T97

9

T98

6

---

Summary for Variable cp_sdaval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sdaval

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

369

1

T96

3

T97

5

T98

11

auto[1]

368

1

T96

9

T97

12

T98

9

---

Summary for Variable cp_txorvden

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txorvden

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

360

1

T96

4

T97

7

T98

7

auto[1]

377

1

T96

8

T97

10

T98

13

---

Summary for Cross cp_txorvden_x_sclval

Samples crossed: cp_txorvden cp_sclval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_txorvden_x_sclval

Bins

cp_txorvden

cp_sclval

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

167

1

T96

1

T97

2

T98

5

auto[0]

auto[1]

193

1

T96

3

T97

5

T98

2

auto[1]

auto[0]

191

1

T96

4

T97

6

T98

9

auto[1]

auto[1]

186

1

T96

4

T97

4

T98

4

---

Summary for Cross cp_txorvden_x_sdaval

Samples crossed: cp_txorvden cp_sdaval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_txorvden_x_sdaval

Bins

cp_txorvden

cp_sdaval

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

170

1

T96

1

T97

3

T98

2

auto[0]

auto[1]

190

1

T96

3

T97

4

T98

5

auto[1]

auto[0]

199

1

T96

2

T97

2

T98

9

auto[1]

auto[1]

178

1

T96

6

T97

8

T98

4