Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24186275	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6925313

1

T1

4401

T2

439

T3

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	30355230	1			T1	32524		T2	1000		T3	165
values[0x0]	377303	1			T1	278		T2	276		T3	25
values[0x1]	379055	1			T1	298		T2	260		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16951364	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14160224

1

T1

13340

T2

722

T3

87

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	111940	1			T1	114		T2	11		T3	1
valid_sources[0x01]	124312	1			T1	121		T2	12		T3	2
valid_sources[0x02]	129914	1			T1	125		T2	3		T3	1
valid_sources[0x03]	125997	1			T1	119		T2	8		T5	1
valid_sources[0x04]	108449	1			T1	128		T2	1		T5	1
valid_sources[0x05]	107106	1			T1	117		T2	8		T6	3
valid_sources[0x06]	111576	1			T1	115		T2	9		T3	3
valid_sources[0x07]	110004	1			T1	127		T2	4		T7	4100
valid_sources[0x08]	113124	1			T1	115		T2	3		T3	1
valid_sources[0x09]	124003	1			T1	94		T3	2		T6	3
valid_sources[0x0a]	136662	1			T1	172		T2	8		T6	3
valid_sources[0x0b]	127798	1			T1	157		T2	11		T3	1
valid_sources[0x0c]	116163	1			T1	102		T2	7		T3	2
valid_sources[0x0d]	165609	1			T1	142		T2	2		T6	1
valid_sources[0x0e]	127455	1			T1	154		T2	3		T3	1
valid_sources[0x0f]	112840	1			T1	164		T2	5		T3	3
valid_sources[0x10]	126472	1			T1	129		T2	5		T6	1
valid_sources[0x11]	117979	1			T1	119		T2	5		T5	11
valid_sources[0x12]	117913	1			T1	122		T2	14		T6	3
valid_sources[0x13]	108117	1			T1	140		T2	7		T5	1
valid_sources[0x14]	125535	1			T1	123		T2	4		T5	6
valid_sources[0x15]	131107	1			T1	139		T2	3		T3	1
valid_sources[0x16]	219139	1			T1	112		T2	4		T6	2
valid_sources[0x17]	103532	1			T1	116		T2	1		T3	1
valid_sources[0x18]	126552	1			T1	122		T2	6		T3	3
valid_sources[0x19]	116251	1			T1	133		T2	4		T3	2
valid_sources[0x1a]	125066	1			T1	137		T2	12		T3	1
valid_sources[0x1b]	123143	1			T1	141		T2	4		T3	1
valid_sources[0x1c]	124792	1			T1	120		T2	6		T6	4
valid_sources[0x1d]	112605	1			T1	136		T2	6		T6	4
valid_sources[0x1e]	164644	1			T1	132		T2	4		T3	1
valid_sources[0x1f]	116790	1			T1	123		T2	7		T7	3797
valid_sources[0x20]	125515	1			T1	136		T2	1		T7	3992
valid_sources[0x21]	119956	1			T1	132		T2	9		T5	2
valid_sources[0x22]	161740	1			T1	169		T2	3		T5	4
valid_sources[0x23]	121444	1			T1	131		T2	7		T5	1
valid_sources[0x24]	119054	1			T1	144		T2	13		T3	1
valid_sources[0x25]	131137	1			T1	127		T2	13		T3	2
valid_sources[0x26]	129913	1			T1	149		T2	7		T5	3
valid_sources[0x27]	122208	1			T1	147		T2	2		T6	4
valid_sources[0x28]	132062	1			T1	156		T2	12		T6	1
valid_sources[0x29]	119423	1			T1	128		T3	1		T6	1
valid_sources[0x2a]	116815	1			T1	125		T2	7		T6	1
valid_sources[0x2b]	108694	1			T1	122		T2	11		T3	1
valid_sources[0x2c]	109313	1			T1	123		T2	4		T3	1
valid_sources[0x2d]	125105	1			T1	97		T2	3		T3	1
valid_sources[0x2e]	104463	1			T1	130		T2	2		T6	3
valid_sources[0x2f]	135184	1			T1	99		T2	5		T3	2
valid_sources[0x30]	110150	1			T1	134		T2	3		T6	3
valid_sources[0x31]	123207	1			T1	88		T2	9		T5	1
valid_sources[0x32]	114943	1			T1	150		T2	2		T3	2
valid_sources[0x33]	116725	1			T1	135		T2	8		T6	3
valid_sources[0x34]	114277	1			T1	119		T2	9		T3	1
valid_sources[0x35]	116344	1			T1	107		T2	8		T6	4
valid_sources[0x36]	122788	1			T1	123		T2	7		T3	1
valid_sources[0x37]	119657	1			T1	121		T2	13		T3	2
valid_sources[0x38]	127186	1			T1	152		T2	14		T6	4
valid_sources[0x39]	109875	1			T1	139		T2	11		T6	5
valid_sources[0x3a]	127301	1			T1	116		T2	4		T5	2
valid_sources[0x3b]	111472	1			T1	134		T2	1		T3	1
valid_sources[0x3c]	103637	1			T1	115		T2	3		T6	1
valid_sources[0x3d]	120368	1			T1	101		T2	11		T3	2
valid_sources[0x3e]	147769	1			T1	114		T2	6		T3	1
valid_sources[0x3f]	121968	1			T1	157		T2	6		T6	4
valid_sources[0x40]	107183	1			T1	87		T2	13		T3	2
valid_sources[0x41]	110168	1			T1	133		T2	3		T3	1
valid_sources[0x42]	126770	1			T1	116		T2	9		T6	4
valid_sources[0x43]	116164	1			T1	120		T2	8		T3	2
valid_sources[0x44]	126144	1			T1	113		T2	6		T7	4461
valid_sources[0x45]	126753	1			T1	110		T2	8		T3	1
valid_sources[0x46]	147371	1			T1	141		T2	13		T5	2
valid_sources[0x47]	121515	1			T1	121		T2	8		T3	4
valid_sources[0x48]	129651	1			T1	139		T2	7		T6	4
valid_sources[0x49]	115242	1			T1	137		T2	6		T5	1
valid_sources[0x4a]	120689	1			T1	105		T2	3		T6	2
valid_sources[0x4b]	110436	1			T1	149		T2	3		T3	3
valid_sources[0x4c]	112427	1			T1	139		T2	2		T3	1
valid_sources[0x4d]	116732	1			T1	148		T2	7		T3	1
valid_sources[0x4e]	119679	1			T1	135		T2	4		T6	2
valid_sources[0x4f]	141766	1			T1	107		T2	5		T3	2
valid_sources[0x50]	147071	1			T1	129		T2	4		T3	1
valid_sources[0x51]	133114	1			T1	134		T2	5		T6	2
valid_sources[0x52]	118143	1			T1	109		T2	1		T3	1
valid_sources[0x53]	110674	1			T1	126		T2	3		T3	2
valid_sources[0x54]	150362	1			T1	133		T2	9		T3	1
valid_sources[0x55]	133692	1			T1	110		T2	6		T3	2
valid_sources[0x56]	135738	1			T1	141		T2	1		T6	1
valid_sources[0x57]	110286	1			T1	138		T2	12		T6	2
valid_sources[0x58]	114932	1			T1	116		T2	7		T6	3
valid_sources[0x59]	111632	1			T1	134		T2	4		T7	4186
valid_sources[0x5a]	123048	1			T1	145		T2	4		T3	1
valid_sources[0x5b]	126523	1			T1	143		T2	1		T6	4
valid_sources[0x5c]	112715	1			T1	98		T2	4		T3	1
valid_sources[0x5d]	112627	1			T1	122		T2	9		T3	1
valid_sources[0x5e]	128442	1			T1	116		T2	7		T6	4
valid_sources[0x5f]	156239	1			T1	136		T2	5		T3	1
valid_sources[0x60]	119436	1			T1	129		T2	7		T3	4
valid_sources[0x61]	144980	1			T1	132		T2	11		T3	2
valid_sources[0x62]	111328	1			T1	131		T2	9		T6	4
valid_sources[0x63]	119779	1			T1	140		T6	4		T7	4123
valid_sources[0x64]	134210	1			T1	142		T2	3		T5	5
valid_sources[0x65]	108323	1			T1	104		T2	3		T3	3
valid_sources[0x66]	133026	1			T1	116		T2	5		T5	2
valid_sources[0x67]	111315	1			T1	135		T2	6		T3	1
valid_sources[0x68]	121240	1			T1	141		T2	9		T3	5
valid_sources[0x69]	125394	1			T1	130		T2	3		T6	1
valid_sources[0x6a]	113745	1			T1	124		T2	3		T6	1
valid_sources[0x6b]	108923	1			T1	125		T2	3		T6	3
valid_sources[0x6c]	118180	1			T1	124		T2	3		T3	2
valid_sources[0x6d]	108881	1			T1	149		T2	8		T3	1
valid_sources[0x6e]	119794	1			T1	118		T2	3		T6	2
valid_sources[0x6f]	117878	1			T1	110		T2	9		T5	4
valid_sources[0x70]	134485	1			T1	134		T2	4		T6	5
valid_sources[0x71]	116790	1			T1	104		T2	8		T3	2
valid_sources[0x72]	127790	1			T1	166		T2	9		T6	5
valid_sources[0x73]	129628	1			T1	137		T2	5		T5	8
valid_sources[0x74]	109641	1			T1	123		T2	3		T6	2
valid_sources[0x75]	115951	1			T1	125		T2	10		T6	2
valid_sources[0x76]	120283	1			T1	130		T2	7		T7	4198
valid_sources[0x77]	120311	1			T1	135		T2	4		T6	4
valid_sources[0x78]	128176	1			T1	113		T2	10		T6	3
valid_sources[0x79]	124482	1			T1	116		T2	7		T3	2
valid_sources[0x7a]	123948	1			T1	128		T5	2		T6	3
valid_sources[0x7b]	140078	1			T1	168		T2	8		T6	7
valid_sources[0x7c]	113397	1			T1	98		T2	6		T3	1
valid_sources[0x7d]	126075	1			T1	134		T2	5		T6	1
valid_sources[0x7e]	139162	1			T1	91		T2	4		T3	3
valid_sources[0x7f]	149255	1			T1	147		T2	5		T6	4
valid_sources[0x80]	110315	1			T1	97		T2	4		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6587177

1

T1

4018

T2

216

T3

14

values[0x0]

all_enables

biggest_size

199588

1

T1

196

T2

145

T3

11

values[0x1]

all_enables

biggest_size

138548

1

T1

187

T2

78

T3

4