Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	346410615	0	0	0
ctrl_rd_A	346410615	1434	0	0
host_fifo_config_rd_A	346410615	4469	0	0
host_nack_handler_timeout_rd_A	346410615	1106	0	0
host_timeout_ctrl_rd_A	346410615	1201	0	0
intr_enable_rd_A	346410615	2717	0	0
ovrd_rd_A	346410615	1993	0	0
target_fifo_config_rd_A	346410615	1130	0	0
target_id_rd_A	346410615	1201	0	0
target_timeout_ctrl_rd_A	346410615	1118	0	0
timeout_ctrl_rd_A	346410615	1159	0	0
timing0_rd_A	346410615	1146	0	0
timing1_rd_A	346410615	1081	0	0
timing2_rd_A	346410615	1045	0	0
timing3_rd_A	346410615	1191	0	0
timing4_rd_A	346410615	1294	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1434	0	0
T100	13189	30	0	0
T101	7003	74	0	0
T102	3369	26	0	0
T103	2781	18	0	0
T104	1897	5	0	0
T105	3285	11	0	0
T106	14036	62	0	0
T107	3831	16	0	0
T108	2877	7	0	0
T109	11033	257	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	4469	0	0
T18	12604	0	0	0
T19	0	111	0	0
T40	12370	0	0	0
T44	223782	0	0	0
T60	85843	0	0	0
T80	277335	120	0	0
T110	0	115	0	0
T111	0	163	0	0
T112	0	216	0	0
T113	0	103	0	0
T114	0	140	0	0
T115	0	165	0	0
T116	0	220	0	0
T117	0	244	0	0
T118	116507	0	0	0
T119	14865	0	0	0
T120	80347	0	0	0
T121	105263	0	0	0
T122	404953	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1106	0	0
T100	13189	16	0	0
T101	7003	23	0	0
T102	3369	30	0	0
T104	1897	4	0	0
T105	3285	9	0	0
T106	14036	18	0	0
T107	3831	30	0	0
T108	2877	16	0	0
T109	11033	206	0	0
T123	3055	10	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1201	0	0
T100	13189	26	0	0
T101	7003	17	0	0
T102	3369	41	0	0
T103	2781	20	0	0
T104	1897	12	0	0
T105	3285	14	0	0
T106	14036	41	0	0
T107	3831	12	0	0
T108	2877	1	0	0
T123	3055	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	2717	0	0
T23	54356	0	0	0
T25	0	9	0	0
T26	102344	18	0	0
T30	0	32	0	0
T32	63126	0	0	0
T38	6476	0	0	0
T45	52511	0	0	0
T78	120146	0	0	0
T79	100918	0	0	0
T99	10570	0	0	0
T100	0	29	0	0
T101	0	227	0	0
T102	0	33	0	0
T103	0	5	0	0
T123	0	2	0	0
T124	0	22	0	0
T125	0	21	0	0
T126	655155	0	0	0
T127	41251	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1993	0	0
T26	102344	0	0	0
T37	158583	0	0	0
T70	162423	0	0	0
T71	41118	0	0	0
T72	68568	0	0	0
T78	120146	0	0	0
T96	1105	42	0	0
T97	0	54	0	0
T126	655155	0	0	0
T127	41251	0	0	0
T128	0	49	0	0
T129	0	78	0	0
T130	0	45	0	0
T131	0	75	0	0
T132	0	28	0	0
T133	0	12	0	0
T134	0	31	0	0
T135	0	31	0	0
T136	103727	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1130	0	0
T100	13189	48	0	0
T101	7003	23	0	0
T102	3369	40	0	0
T103	2781	3	0	0
T104	1897	15	0	0
T105	3285	34	0	0
T106	14036	50	0	0
T107	3831	2	0	0
T108	2877	2	0	0
T123	3055	53	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1201	0	0
T100	13189	35	0	0
T101	7003	43	0	0
T102	3369	6	0	0
T103	2781	28	0	0
T104	1897	9	0	0
T105	3285	16	0	0
T106	14036	14	0	0
T107	3831	19	0	0
T108	2877	38	0	0
T123	3055	7	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1118	0	0
T100	13189	22	0	0
T101	7003	34	0	0
T102	3369	18	0	0
T103	2781	19	0	0
T104	1897	8	0	0
T105	3285	20	0	0
T106	14036	29	0	0
T107	3831	19	0	0
T108	2877	9	0	0
T123	3055	12	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1159	0	0
T100	13189	74	0	0
T101	7003	18	0	0
T102	3369	14	0	0
T103	2781	10	0	0
T104	1897	13	0	0
T105	3285	27	0	0
T106	14036	14	0	0
T107	3831	41	0	0
T108	2877	8	0	0
T123	3055	20	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1146	0	0
T100	13189	43	0	0
T101	7003	40	0	0
T102	3369	37	0	0
T103	2781	27	0	0
T104	1897	2	0	0
T105	3285	15	0	0
T106	14036	39	0	0
T107	3831	18	0	0
T108	2877	27	0	0
T123	3055	18	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1081	0	0
T100	13189	21	0	0
T101	7003	35	0	0
T102	3369	20	0	0
T103	2781	25	0	0
T104	1897	8	0	0
T105	3285	17	0	0
T106	14036	41	0	0
T107	3831	7	0	0
T108	2877	5	0	0
T123	3055	8	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1045	0	0
T100	13189	21	0	0
T101	7003	30	0	0
T102	3369	2	0	0
T103	2781	24	0	0
T104	1897	5	0	0
T105	3285	16	0	0
T106	14036	17	0	0
T107	3831	18	0	0
T108	2877	7	0	0
T123	3055	8	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1191	0	0
T100	13189	51	0	0
T101	7003	35	0	0
T102	3369	3	0	0
T103	2781	28	0	0
T104	1897	5	0	0
T105	3285	28	0	0
T106	14036	56	0	0
T107	3831	33	0	0
T108	2877	22	0	0
T123	3055	29	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346410615	1294	0	0
T100	13189	16	0	0
T101	7003	43	0	0
T102	3369	49	0	0
T103	2781	4	0	0
T104	1897	7	0	0
T105	3285	25	0	0
T106	14036	17	0	0
T107	3831	4	0	0
T108	2877	17	0	0
T123	3055	35	0	0