Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24165300	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7059868

1

T1

36308

T2

12

T3

792

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	30415656	1			T1	146447		T2	3		T3	2195
values[0x0]	404617	1			T1	451		T2	9		T3	59
values[0x1]	404895	1			T1	456		T2	7		T3	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16945687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14279481

1

T1

68618

T2

14

T3

1168

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	170763	1			T1	689		T4	4		T5	4
valid_sources[0x01]	123988	1			T1	626		T5	3		T7	655
valid_sources[0x02]	120665	1			T1	454		T2	1		T5	3
valid_sources[0x03]	118145	1			T1	431		T5	1		T7	626
valid_sources[0x04]	110993	1			T1	1133		T5	1		T7	760
valid_sources[0x05]	125153	1			T1	709		T4	1		T5	2
valid_sources[0x06]	126353	1			T1	624		T5	5		T7	636
valid_sources[0x07]	116675	1			T1	640		T5	5		T7	659
valid_sources[0x08]	120589	1			T1	412		T5	5		T7	714
valid_sources[0x09]	116215	1			T1	656		T7	797		T8	5
valid_sources[0x0a]	113347	1			T1	1012		T5	2		T7	741
valid_sources[0x0b]	123966	1			T1	558		T5	5		T7	590
valid_sources[0x0c]	125866	1			T1	812		T4	1		T5	4
valid_sources[0x0d]	115024	1			T1	307		T5	2		T7	583
valid_sources[0x0e]	122677	1			T1	561		T5	5		T7	582
valid_sources[0x0f]	116169	1			T1	730		T5	5		T7	704
valid_sources[0x10]	128522	1			T1	793		T5	1		T7	724
valid_sources[0x11]	149020	1			T1	598		T2	3		T5	6
valid_sources[0x12]	113019	1			T1	393		T5	5		T7	859
valid_sources[0x13]	109269	1			T1	381		T5	4		T7	746
valid_sources[0x14]	115466	1			T1	651		T5	8		T7	637
valid_sources[0x15]	106342	1			T1	435		T5	6		T7	665
valid_sources[0x16]	118874	1			T1	441		T5	6		T6	2
valid_sources[0x17]	130473	1			T1	529		T5	6		T7	723
valid_sources[0x18]	110607	1			T1	738		T4	1		T5	3
valid_sources[0x19]	123086	1			T1	395		T5	4		T7	650
valid_sources[0x1a]	122191	1			T1	1100		T5	2		T7	740
valid_sources[0x1b]	114308	1			T1	560		T5	4		T7	680
valid_sources[0x1c]	123966	1			T1	573		T5	5		T7	715
valid_sources[0x1d]	123335	1			T1	718		T5	6		T7	628
valid_sources[0x1e]	118798	1			T1	495		T5	3		T7	782
valid_sources[0x1f]	119631	1			T1	619		T5	3		T7	620
valid_sources[0x20]	131828	1			T1	584		T5	3		T7	534
valid_sources[0x21]	108139	1			T1	395		T5	3		T7	681
valid_sources[0x22]	119464	1			T1	591		T2	1		T5	1
valid_sources[0x23]	113752	1			T1	313		T5	2		T7	653
valid_sources[0x24]	121145	1			T1	379		T2	3		T5	1
valid_sources[0x25]	126051	1			T1	833		T5	5		T7	703
valid_sources[0x26]	131155	1			T1	489		T5	1		T7	701
valid_sources[0x27]	128982	1			T1	373		T5	5		T7	696
valid_sources[0x28]	111007	1			T1	688		T5	8		T7	663
valid_sources[0x29]	112434	1			T1	605		T5	5		T7	670
valid_sources[0x2a]	112164	1			T1	667		T5	5		T7	639
valid_sources[0x2b]	138467	1			T1	353		T5	4		T7	784
valid_sources[0x2c]	143121	1			T1	637		T5	1		T7	608
valid_sources[0x2d]	116516	1			T1	674		T5	2		T7	672
valid_sources[0x2e]	120391	1			T1	770		T5	7		T7	737
valid_sources[0x2f]	141399	1			T1	824		T5	5		T7	729
valid_sources[0x30]	123357	1			T1	538		T5	5		T7	678
valid_sources[0x31]	113857	1			T1	610		T5	4		T7	740
valid_sources[0x32]	104301	1			T1	273		T5	2		T7	648
valid_sources[0x33]	126087	1			T1	675		T5	3		T7	585
valid_sources[0x34]	118340	1			T1	499		T5	4		T7	636
valid_sources[0x35]	120457	1			T1	660		T5	3		T7	629
valid_sources[0x36]	134525	1			T1	269		T7	790		T9	3
valid_sources[0x37]	137592	1			T1	716		T5	3		T7	661
valid_sources[0x38]	134787	1			T1	519		T5	6		T7	514
valid_sources[0x39]	117559	1			T1	607		T5	4		T7	680
valid_sources[0x3a]	118096	1			T1	485		T7	572		T8	3
valid_sources[0x3b]	113022	1			T1	161		T5	2		T7	772
valid_sources[0x3c]	129692	1			T1	611		T5	5		T7	832
valid_sources[0x3d]	120463	1			T1	388		T5	4		T7	751
valid_sources[0x3e]	125293	1			T1	521		T5	7		T7	753
valid_sources[0x3f]	108823	1			T1	379		T5	4		T7	734
valid_sources[0x40]	107714	1			T1	190		T5	4		T7	524
valid_sources[0x41]	107017	1			T1	772		T5	1		T7	707
valid_sources[0x42]	117631	1			T1	654		T5	4		T7	684
valid_sources[0x43]	121164	1			T1	946		T5	3		T7	731
valid_sources[0x44]	121769	1			T1	263		T5	8		T7	652
valid_sources[0x45]	120121	1			T1	538		T5	5		T7	547
valid_sources[0x46]	122548	1			T1	284		T5	2		T7	638
valid_sources[0x47]	121005	1			T1	720		T5	5		T7	734
valid_sources[0x48]	116776	1			T1	709		T5	3		T7	615
valid_sources[0x49]	141481	1			T1	556		T5	6		T7	680
valid_sources[0x4a]	109318	1			T1	591		T5	6		T7	583
valid_sources[0x4b]	114369	1			T1	1201		T7	634		T8	3
valid_sources[0x4c]	140188	1			T1	570		T5	8		T7	702
valid_sources[0x4d]	124443	1			T1	1040		T5	2		T7	657
valid_sources[0x4e]	132296	1			T1	544		T5	5		T7	500
valid_sources[0x4f]	115963	1			T1	452		T5	2		T7	663
valid_sources[0x50]	124815	1			T1	433		T5	8		T7	551
valid_sources[0x51]	114030	1			T1	982		T5	5		T7	759
valid_sources[0x52]	117801	1			T1	302		T4	3		T5	2
valid_sources[0x53]	128087	1			T1	647		T5	2		T7	678
valid_sources[0x54]	137012	1			T1	294		T7	646		T8	4
valid_sources[0x55]	133208	1			T1	721		T5	6		T7	596
valid_sources[0x56]	131934	1			T1	442		T5	4		T7	628
valid_sources[0x57]	113432	1			T1	444		T5	2		T7	714
valid_sources[0x58]	118141	1			T1	632		T5	1		T7	780
valid_sources[0x59]	130091	1			T1	554		T5	4		T7	669
valid_sources[0x5a]	117967	1			T1	451		T5	7		T7	645
valid_sources[0x5b]	110360	1			T1	614		T5	4		T7	723
valid_sources[0x5c]	122082	1			T1	533		T5	2		T7	870
valid_sources[0x5d]	116284	1			T1	808		T5	8		T7	633
valid_sources[0x5e]	113241	1			T1	521		T5	5		T7	633
valid_sources[0x5f]	113035	1			T1	444		T5	5		T7	651
valid_sources[0x60]	125398	1			T1	395		T5	5		T7	681
valid_sources[0x61]	119164	1			T1	404		T5	6		T7	719
valid_sources[0x62]	128456	1			T1	660		T5	3		T7	733
valid_sources[0x63]	119731	1			T1	677		T5	3		T7	829
valid_sources[0x64]	112229	1			T1	513		T5	3		T7	653
valid_sources[0x65]	108434	1			T1	541		T5	5		T7	782
valid_sources[0x66]	121731	1			T1	936		T5	3		T7	783
valid_sources[0x67]	123177	1			T1	599		T5	7		T7	611
valid_sources[0x68]	117189	1			T1	309		T5	1		T7	544
valid_sources[0x69]	174176	1			T1	541		T5	5		T7	750
valid_sources[0x6a]	119905	1			T1	983		T5	11		T7	686
valid_sources[0x6b]	129367	1			T1	559		T5	4		T7	706
valid_sources[0x6c]	106974	1			T1	469		T5	1		T7	666
valid_sources[0x6d]	111838	1			T1	945		T4	1		T5	4
valid_sources[0x6e]	119220	1			T1	523		T5	1		T7	706
valid_sources[0x6f]	114867	1			T1	563		T5	4		T7	691
valid_sources[0x70]	124509	1			T1	437		T5	5		T7	707
valid_sources[0x71]	147713	1			T1	569		T5	3		T7	639
valid_sources[0x72]	115738	1			T1	693		T5	3		T7	728
valid_sources[0x73]	112562	1			T1	742		T5	6		T7	721
valid_sources[0x74]	118832	1			T1	737		T5	2		T7	708
valid_sources[0x75]	113144	1			T1	820		T5	4		T7	769
valid_sources[0x76]	124868	1			T1	633		T5	3		T7	734
valid_sources[0x77]	108161	1			T1	584		T5	5		T7	630
valid_sources[0x78]	116943	1			T1	497		T5	4		T7	762
valid_sources[0x79]	128634	1			T1	643		T2	2		T5	2
valid_sources[0x7a]	109444	1			T1	284		T5	9		T7	680
valid_sources[0x7b]	113766	1			T1	761		T5	5		T7	853
valid_sources[0x7c]	111629	1			T1	642		T5	2		T7	659
valid_sources[0x7d]	135943	1			T1	340		T5	7		T7	839
valid_sources[0x7e]	105940	1			T1	564		T5	4		T7	660
valid_sources[0x7f]	120558	1			T1	583		T5	5		T7	621
valid_sources[0x80]	129926	1			T1	420		T5	1		T7	681

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6701170

1

T1

35840

T2

2

T3

742

values[0x0]

all_enables

biggest_size

213104

1

T1

273

T2

7

T3

32

values[0x1]

all_enables

biggest_size

145594

1

T1

195

T2

3

T3

18