Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	403901785	0	0	0
ctrl_rd_A	403901785	1331	0	0
host_fifo_config_rd_A	403901785	4418	0	0
host_nack_handler_timeout_rd_A	403901785	598	0	0
host_timeout_ctrl_rd_A	403901785	553	0	0
intr_enable_rd_A	403901785	2318	0	0
ovrd_rd_A	403901785	1419	0	0
target_fifo_config_rd_A	403901785	673	0	0
target_id_rd_A	403901785	738	0	0
target_timeout_ctrl_rd_A	403901785	616	0	0
timeout_ctrl_rd_A	403901785	831	0	0
timing0_rd_A	403901785	680	0	0
timing1_rd_A	403901785	616	0	0
timing2_rd_A	403901785	592	0	0
timing3_rd_A	403901785	682	0	0
timing4_rd_A	403901785	712	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	1331	0	0
T98	2331	18	0	0
T99	1325	2	0	0
T100	5520	63	0	0
T101	15791	420	0	0
T102	5260	17	0	0
T103	1803	27	0	0
T104	8293	58	0	0
T105	1920	9	0	0
T106	1097	2	0	0
T107	2645	41	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	4418	0	0
T7	182065	430	0	0
T8	48792	0	0	0
T9	60255	0	0	0
T10	2081	0	0	0
T14	241687	0	0	0
T20	355126	0	0	0
T40	10154	0	0	0
T50	713660	0	0	0
T64	69109	0	0	0
T70	49549	0	0	0
T85	0	197	0	0
T108	0	147	0	0
T109	0	61	0	0
T110	0	150	0	0
T111	0	110	0	0
T112	0	147	0	0
T113	0	168	0	0
T114	0	182	0	0
T115	0	173	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	598	0	0
T98	2331	6	0	0
T99	1325	9	0	0
T100	5520	71	0	0
T101	15791	86	0	0
T103	1803	3	0	0
T105	1920	6	0	0
T106	1097	2	0	0
T107	2645	13	0	0
T116	3650	9	0	0
T117	2172	6	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	553	0	0
T99	1325	2	0	0
T100	5520	86	0	0
T101	15791	98	0	0
T102	5260	7	0	0
T103	1803	4	0	0
T104	8293	4	0	0
T105	1920	3	0	0
T106	1097	1	0	0
T107	2645	10	0	0
T116	3650	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	2318	0	0
T28	498832	22	0	0
T31	19971	0	0	0
T98	0	3	0	0
T99	0	43	0	0
T100	0	65	0	0
T101	0	604	0	0
T118	0	16	0	0
T119	0	25	0	0
T120	0	52	0	0
T121	0	7	0	0
T122	0	21	0	0
T123	144836	0	0	0
T124	16860	0	0	0
T125	13957	0	0	0
T126	15286	0	0	0
T127	38272	0	0	0
T128	27062	0	0	0
T129	11568	0	0	0
T130	1291	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	1419	0	0
T10	2081	44	0	0
T14	241687	0	0	0
T20	355126	0	0	0
T40	10154	0	0	0
T50	713660	0	0	0
T55	49521	0	0	0
T56	43330	0	0	0
T58	64532	0	0	0
T64	69109	0	0	0
T70	49549	0	0	0
T77	0	45	0	0
T87	0	51	0	0
T94	0	20	0	0
T131	0	62	0	0
T132	0	23	0	0
T133	0	46	0	0
T134	0	22	0	0
T135	0	76	0	0
T136	0	27	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	673	0	0
T98	2331	9	0	0
T99	1325	6	0	0
T100	5520	61	0	0
T101	15791	99	0	0
T102	5260	8	0	0
T103	1803	23	0	0
T104	8293	15	0	0
T105	1920	8	0	0
T106	1097	6	0	0
T116	3650	30	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	738	0	0
T98	2331	21	0	0
T99	1325	6	0	0
T100	5520	59	0	0
T101	15791	145	0	0
T102	5260	9	0	0
T103	1803	6	0	0
T104	8293	9	0	0
T105	1920	25	0	0
T106	1097	9	0	0
T116	3650	7	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	616	0	0
T98	2331	8	0	0
T99	1325	4	0	0
T100	5520	46	0	0
T101	15791	107	0	0
T102	5260	17	0	0
T103	1803	11	0	0
T104	8293	14	0	0
T105	1920	8	0	0
T106	1097	2	0	0
T116	3650	20	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	831	0	0
T98	2331	16	0	0
T100	5520	64	0	0
T101	15791	163	0	0
T102	5260	23	0	0
T103	1803	19	0	0
T104	8293	13	0	0
T105	1920	22	0	0
T106	1097	13	0	0
T107	2645	13	0	0
T116	3650	16	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	680	0	0
T98	2331	5	0	0
T99	1325	10	0	0
T100	5520	71	0	0
T101	15791	114	0	0
T102	5260	32	0	0
T103	1803	19	0	0
T104	8293	21	0	0
T105	1920	2	0	0
T106	1097	7	0	0
T116	3650	11	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	616	0	0
T98	2331	12	0	0
T99	1325	5	0	0
T100	5520	60	0	0
T101	15791	102	0	0
T102	5260	35	0	0
T103	1803	16	0	0
T104	8293	12	0	0
T105	1920	14	0	0
T106	1097	16	0	0
T116	3650	8	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	592	0	0
T98	2331	5	0	0
T99	1325	2	0	0
T100	5520	53	0	0
T101	15791	127	0	0
T102	5260	23	0	0
T103	1803	22	0	0
T104	8293	14	0	0
T105	1920	5	0	0
T107	2645	12	0	0
T116	3650	9	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	682	0	0
T98	2331	7	0	0
T99	1325	7	0	0
T100	5520	44	0	0
T101	15791	115	0	0
T102	5260	35	0	0
T103	1803	6	0	0
T104	8293	38	0	0
T105	1920	7	0	0
T106	1097	1	0	0
T116	3650	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403901785	712	0	0
T98	2331	7	0	0
T99	1325	2	0	0
T100	5520	62	0	0
T101	15791	144	0	0
T102	5260	12	0	0
T103	1803	12	0	0
T104	8293	4	0	0
T105	1920	2	0	0
T106	1097	7	0	0
T116	3650	10	0	0