Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	340	1			T1	8		T3	1		T7	5
all_pins[1]	340	1			T1	8		T3	1		T7	5
all_pins[2]	340	1			T1	8		T3	1		T7	5
all_pins[3]	340	1			T1	8		T3	1		T7	5
all_pins[4]	340	1			T1	8		T3	1		T7	5
all_pins[5]	340	1			T1	8		T3	1		T7	5
all_pins[6]	340	1			T1	8		T3	1		T7	5
all_pins[7]	340	1			T1	8		T3	1		T7	5
all_pins[8]	340	1			T1	8		T3	1		T7	5
all_pins[9]	340	1			T1	8		T3	1		T7	5
all_pins[10]	340	1			T1	8		T3	1		T7	5
all_pins[11]	340	1			T1	8		T3	1		T7	5
all_pins[12]	340	1			T1	8		T3	1		T7	5
all_pins[13]	340	1			T1	8		T3	1		T7	5
all_pins[14]	340	1			T1	8		T3	1		T7	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4259	1			T1	94		T3	15		T7	64
values[0x1]	841	1			T1	26		T7	11		T11	21
transitions[0x0=>0x1]	664	1			T1	18		T7	10		T11	14
transitions[0x1=>0x0]	670	1			T1	18		T7	10		T11	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	283	1			T1	7		T3	1		T7	5
all_pins[0]	values[0x1]	57	1			T1	1		T11	1		T12	1
all_pins[0]	transitions[0x0=>0x1]	45	1			T1	1		T11	1		T12	1
all_pins[0]	transitions[0x1=>0x0]	41	1			T1	2		T11	1		T12	1
all_pins[1]	values[0x0]	287	1			T1	6		T3	1		T7	5
all_pins[1]	values[0x1]	53	1			T1	2		T11	1		T12	1
all_pins[1]	transitions[0x0=>0x1]	46	1			T1	2		T11	1		T12	1
all_pins[1]	transitions[0x1=>0x0]	38	1			T1	1		T11	2		T12	1
all_pins[2]	values[0x0]	295	1			T1	7		T3	1		T7	5
all_pins[2]	values[0x1]	45	1			T1	1		T11	2		T12	1
all_pins[2]	transitions[0x0=>0x1]	38	1			T1	1		T12	1		T70	1
all_pins[2]	transitions[0x1=>0x0]	46	1			T1	4		T11	1		T12	3
all_pins[3]	values[0x0]	287	1			T1	4		T3	1		T7	5
all_pins[3]	values[0x1]	53	1			T1	4		T11	3		T12	3
all_pins[3]	transitions[0x0=>0x1]	44	1			T1	4		T11	2		T12	3
all_pins[3]	transitions[0x1=>0x0]	40	1			T1	1		T7	1		T11	1
all_pins[4]	values[0x0]	291	1			T1	7		T3	1		T7	4
all_pins[4]	values[0x1]	49	1			T1	1		T7	1		T11	2
all_pins[4]	transitions[0x0=>0x1]	36	1			T11	2		T12	1		T71	1
all_pins[4]	transitions[0x1=>0x0]	57	1			T1	2		T7	3		T21	2
all_pins[5]	values[0x0]	270	1			T1	5		T3	1		T7	1
all_pins[5]	values[0x1]	70	1			T1	3		T7	4		T21	3
all_pins[5]	transitions[0x0=>0x1]	56	1			T1	2		T7	4		T21	3
all_pins[5]	transitions[0x1=>0x0]	38	1			T11	2		T12	4		T21	1
all_pins[6]	values[0x0]	288	1			T1	7		T3	1		T7	5
all_pins[6]	values[0x1]	52	1			T1	1		T11	2		T12	4
all_pins[6]	transitions[0x0=>0x1]	37	1			T12	2		T21	1		T50	1
all_pins[6]	transitions[0x1=>0x0]	48	1			T1	2		T7	1		T11	1
all_pins[7]	values[0x0]	277	1			T1	5		T3	1		T7	4
all_pins[7]	values[0x1]	63	1			T1	3		T7	1		T11	3
all_pins[7]	transitions[0x0=>0x1]	53	1			T1	3		T7	1		T11	3
all_pins[7]	transitions[0x1=>0x0]	45	1			T1	2		T11	1		T70	1
all_pins[8]	values[0x0]	285	1			T1	6		T3	1		T7	5
all_pins[8]	values[0x1]	55	1			T1	2		T11	1		T12	2
all_pins[8]	transitions[0x0=>0x1]	44	1			T1	2		T11	1		T12	2
all_pins[8]	transitions[0x1=>0x0]	53	1			T1	1		T11	1		T12	1
all_pins[9]	values[0x0]	276	1			T1	7		T3	1		T7	5
all_pins[9]	values[0x1]	64	1			T1	1		T11	1		T12	1
all_pins[9]	transitions[0x0=>0x1]	47	1			T11	1		T12	1		T70	1
all_pins[9]	transitions[0x1=>0x0]	40	1			T7	1		T11	1		T21	1
all_pins[10]	values[0x0]	283	1			T1	7		T3	1		T7	4
all_pins[10]	values[0x1]	57	1			T1	1		T7	1		T11	1
all_pins[10]	transitions[0x0=>0x1]	47	1			T1	1		T7	1		T21	1
all_pins[10]	transitions[0x1=>0x0]	46	1			T1	1		T7	2		T11	1
all_pins[11]	values[0x0]	284	1			T1	7		T3	1		T7	3
all_pins[11]	values[0x1]	56	1			T1	1		T7	2		T11	2
all_pins[11]	transitions[0x0=>0x1]	45	1			T7	2		T11	1		T12	3
all_pins[11]	transitions[0x1=>0x0]	33	1			T71	1		T50	3		T72	1
all_pins[12]	values[0x0]	296	1			T1	7		T3	1		T7	5
all_pins[12]	values[0x1]	44	1			T1	1		T11	1		T71	1
all_pins[12]	transitions[0x0=>0x1]	37	1			T1	1		T11	1		T71	1
all_pins[12]	transitions[0x1=>0x0]	61	1			T1	2		T7	1		T11	1
all_pins[13]	values[0x0]	272	1			T1	6		T3	1		T7	4
all_pins[13]	values[0x1]	68	1			T1	2		T7	1		T11	1
all_pins[13]	transitions[0x0=>0x1]	53	1			T7	1		T11	1		T21	2
all_pins[13]	transitions[0x1=>0x0]	40	1			T7	1		T12	1		T50	1
all_pins[14]	values[0x0]	285	1			T1	6		T3	1		T7	4
all_pins[14]	values[0x1]	55	1			T1	2		T7	1		T12	1
all_pins[14]	transitions[0x0=>0x1]	36	1			T1	1		T7	1		T12	1
all_pins[14]	transitions[0x1=>0x0]	44	1			T11	1		T12	1		T21	1