Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
52.66 40.66 40.68 90.72 0.00 42.98 99.68 53.89


Total tests in report: 165
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
45.41 45.41 38.76 38.76 36.17 36.17 91.07 91.07 0.00 0.00 41.28 41.28 96.18 96.18 14.42 14.42 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.212008960
50.47 5.06 40.13 1.38 38.50 2.33 94.79 3.72 0.00 0.00 42.84 1.56 96.18 0.00 40.84 26.42 /workspace/coverage/cover_reg_top/22.i2c_intr_test.4040154049
51.74 1.27 40.17 0.03 39.86 1.35 95.78 0.99 0.00 0.00 42.91 0.07 97.45 1.27 46.00 5.16 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.738853683
52.24 0.50 40.62 0.46 39.97 0.11 96.28 0.50 0.00 0.00 42.91 0.00 99.04 1.59 46.84 0.84 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.829452243
52.69 0.45 40.62 0.00 39.97 0.00 96.28 0.00 0.00 0.00 42.91 0.00 99.04 0.00 50.00 3.16 /workspace/coverage/cover_reg_top/33.i2c_intr_test.116888270
53.02 0.34 40.66 0.03 40.31 0.34 97.02 0.74 0.00 0.00 42.98 0.07 99.36 0.32 50.84 0.84 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.419587538
53.17 0.15 40.66 0.00 40.31 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.36 0.00 51.89 1.05 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3538507213
53.27 0.09 40.66 0.00 40.42 0.11 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.32 52.11 0.21 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3141980918
53.36 0.09 40.66 0.00 40.42 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 52.74 0.63 /workspace/coverage/cover_reg_top/3.i2c_intr_test.388905839
53.42 0.06 40.66 0.00 40.42 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.16 0.42 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.592165546
53.45 0.04 40.66 0.00 40.46 0.04 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.37 0.21 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2452382475
53.48 0.03 40.66 0.00 40.46 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.58 0.21 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2684315665
53.51 0.03 40.66 0.00 40.46 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.79 0.21 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.376742077
53.53 0.02 40.66 0.00 40.46 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.89 0.11 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2972690852
53.54 0.01 40.66 0.00 40.53 0.08 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.89 0.00 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1469810883
53.55 0.01 40.66 0.00 40.61 0.08 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.89 0.00 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2056753326
53.55 0.01 40.66 0.00 40.65 0.04 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.89 0.00 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1568916353
53.56 0.01 40.66 0.00 40.68 0.04 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.89 0.00 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2801981322

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3656055395
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1867696441
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.485821127
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3955772327
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3884641787
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1019537569
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.130550948
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3869472131
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1159331196
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.1598427884
/workspace/coverage/cover_reg_top/1.i2c_intr_test.3472338424
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1722649608
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3823285488
/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.794083759
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1409437949
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.2376485591
/workspace/coverage/cover_reg_top/10.i2c_intr_test.4162883815
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.3595112076
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1329270254
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3235579603
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.558604582
/workspace/coverage/cover_reg_top/11.i2c_intr_test.3549548903
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.276245629
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.2095000851
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3370380878
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.2743243470
/workspace/coverage/cover_reg_top/12.i2c_intr_test.2631593452
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1647720260
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.1686672662
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3802292155
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.420799701
/workspace/coverage/cover_reg_top/13.i2c_intr_test.3480060775
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2388068817
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.3411081757
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4235257366
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.3991386193
/workspace/coverage/cover_reg_top/14.i2c_intr_test.3897655257
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2900411066
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.422544994
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2595924700
/workspace/coverage/cover_reg_top/15.i2c_intr_test.3289670807
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1986445576
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.2538756341
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2788290114
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1348268203
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3835552453
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.248043594
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2868266067
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.855923025
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.1652353092
/workspace/coverage/cover_reg_top/17.i2c_intr_test.1956280380
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1649873545
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.561206327
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3524445241
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2339574757
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3554940525
/workspace/coverage/cover_reg_top/18.i2c_intr_test.4165033638
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4238272210
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.3943605203
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.762288469
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.895701933
/workspace/coverage/cover_reg_top/19.i2c_intr_test.2566318331
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.8120256
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.3819343291
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3228976662
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3263826487
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2335819631
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.854298946
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2720569015
/workspace/coverage/cover_reg_top/2.i2c_intr_test.3340311997
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2007757023
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.2167614172
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.463284432
/workspace/coverage/cover_reg_top/20.i2c_intr_test.3346860670
/workspace/coverage/cover_reg_top/21.i2c_intr_test.2832291255
/workspace/coverage/cover_reg_top/23.i2c_intr_test.1152310737
/workspace/coverage/cover_reg_top/24.i2c_intr_test.1717748308
/workspace/coverage/cover_reg_top/25.i2c_intr_test.2034177927
/workspace/coverage/cover_reg_top/26.i2c_intr_test.1770236275
/workspace/coverage/cover_reg_top/27.i2c_intr_test.1143682404
/workspace/coverage/cover_reg_top/28.i2c_intr_test.2764794151
/workspace/coverage/cover_reg_top/29.i2c_intr_test.525601734
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3745021410
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1040235667
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.4161980252
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.159575580
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.235937809
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3377028456
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.3031599479
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2700317683
/workspace/coverage/cover_reg_top/30.i2c_intr_test.794056292
/workspace/coverage/cover_reg_top/31.i2c_intr_test.3896500944
/workspace/coverage/cover_reg_top/32.i2c_intr_test.3690875194
/workspace/coverage/cover_reg_top/34.i2c_intr_test.1299436852
/workspace/coverage/cover_reg_top/35.i2c_intr_test.303450550
/workspace/coverage/cover_reg_top/36.i2c_intr_test.2495566845
/workspace/coverage/cover_reg_top/37.i2c_intr_test.2455857999
/workspace/coverage/cover_reg_top/38.i2c_intr_test.638310959
/workspace/coverage/cover_reg_top/39.i2c_intr_test.3608282033
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3647987091
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3374426575
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2666769686
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1083197477
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.1630858648
/workspace/coverage/cover_reg_top/4.i2c_intr_test.70835033
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1004060920
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.826184366
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1878979820
/workspace/coverage/cover_reg_top/40.i2c_intr_test.4199101114
/workspace/coverage/cover_reg_top/41.i2c_intr_test.2080668581
/workspace/coverage/cover_reg_top/42.i2c_intr_test.870207467
/workspace/coverage/cover_reg_top/43.i2c_intr_test.3957199592
/workspace/coverage/cover_reg_top/44.i2c_intr_test.1437367166
/workspace/coverage/cover_reg_top/45.i2c_intr_test.719181424
/workspace/coverage/cover_reg_top/46.i2c_intr_test.3203218786
/workspace/coverage/cover_reg_top/47.i2c_intr_test.3664744296
/workspace/coverage/cover_reg_top/48.i2c_intr_test.141052986
/workspace/coverage/cover_reg_top/49.i2c_intr_test.2468457398
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3283449020
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3822192490
/workspace/coverage/cover_reg_top/5.i2c_intr_test.1397369881
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.722982400
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.2717714388
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1998716196
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.880347994
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.2549296186
/workspace/coverage/cover_reg_top/6.i2c_intr_test.636635441
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.4010562164
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1803082861
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3834646851
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3672983784
/workspace/coverage/cover_reg_top/7.i2c_intr_test.524518377
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.280207748
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.360983717
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2446266679
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.291010683
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.752829179
/workspace/coverage/cover_reg_top/8.i2c_intr_test.323924484
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3952037344
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.71076784
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.898645466
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3073511393
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.386957585
/workspace/coverage/cover_reg_top/9.i2c_intr_test.4151677316
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1962986747
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.2839529427
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2279502825



Total test records in report: 165
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/22.i2c_intr_test.4040154049 Aug 03 04:31:40 PM PDT 24 Aug 03 04:31:41 PM PDT 24 26735505 ps
T2 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1083197477 Aug 03 04:31:19 PM PDT 24 Aug 03 04:31:21 PM PDT 24 388207913 ps
T3 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.738853683 Aug 03 04:31:13 PM PDT 24 Aug 03 04:31:16 PM PDT 24 112493672 ps
T7 /workspace/coverage/cover_reg_top/42.i2c_intr_test.870207467 Aug 03 04:31:48 PM PDT 24 Aug 03 04:31:49 PM PDT 24 28439004 ps
T8 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3647987091 Aug 03 04:31:21 PM PDT 24 Aug 03 04:31:22 PM PDT 24 55906011 ps
T4 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.212008960 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:19 PM PDT 24 180918578 ps
T9 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1019537569 Aug 03 04:31:20 PM PDT 24 Aug 03 04:31:22 PM PDT 24 191837926 ps
T5 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1986445576 Aug 03 04:31:32 PM PDT 24 Aug 03 04:31:34 PM PDT 24 252116100 ps
T11 /workspace/coverage/cover_reg_top/45.i2c_intr_test.719181424 Aug 03 04:31:47 PM PDT 24 Aug 03 04:31:48 PM PDT 24 84766063 ps
T6 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.485821127 Aug 03 04:31:11 PM PDT 24 Aug 03 04:31:12 PM PDT 24 124052237 ps
T13 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3943605203 Aug 03 04:31:31 PM PDT 24 Aug 03 04:31:34 PM PDT 24 45046407 ps
T12 /workspace/coverage/cover_reg_top/33.i2c_intr_test.116888270 Aug 03 04:31:48 PM PDT 24 Aug 03 04:31:49 PM PDT 24 24587400 ps
T10 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.276245629 Aug 03 04:31:25 PM PDT 24 Aug 03 04:31:26 PM PDT 24 171331808 ps
T21 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3480060775 Aug 03 04:31:25 PM PDT 24 Aug 03 04:31:26 PM PDT 24 17777126 ps
T14 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.826184366 Aug 03 04:31:19 PM PDT 24 Aug 03 04:31:20 PM PDT 24 165610768 ps
T15 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.4010562164 Aug 03 04:31:19 PM PDT 24 Aug 03 04:31:20 PM PDT 24 159295658 ps
T22 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3377028456 Aug 03 04:31:19 PM PDT 24 Aug 03 04:31:20 PM PDT 24 23901077 ps
T16 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3595112076 Aug 03 04:31:25 PM PDT 24 Aug 03 04:31:28 PM PDT 24 294741696 ps
T17 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.422544994 Aug 03 04:31:34 PM PDT 24 Aug 03 04:31:35 PM PDT 24 255538441 ps
T23 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1962986747 Aug 03 04:31:28 PM PDT 24 Aug 03 04:31:30 PM PDT 24 47715215 ps
T18 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3802292155 Aug 03 04:31:33 PM PDT 24 Aug 03 04:31:34 PM PDT 24 119055336 ps
T24 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2684315665 Aug 03 04:31:13 PM PDT 24 Aug 03 04:31:14 PM PDT 24 19566576 ps
T25 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.829452243 Aug 03 04:31:23 PM PDT 24 Aug 03 04:31:23 PM PDT 24 19485687 ps
T54 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4235257366 Aug 03 04:31:29 PM PDT 24 Aug 03 04:31:31 PM PDT 24 139850204 ps
T41 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.280207748 Aug 03 04:31:26 PM PDT 24 Aug 03 04:31:27 PM PDT 24 57742459 ps
T19 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3283449020 Aug 03 04:31:20 PM PDT 24 Aug 03 04:31:22 PM PDT 24 27584330 ps
T70 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3289670807 Aug 03 04:31:31 PM PDT 24 Aug 03 04:31:32 PM PDT 24 17979140 ps
T26 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1348268203 Aug 03 04:31:34 PM PDT 24 Aug 03 04:31:35 PM PDT 24 26860518 ps
T20 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3073511393 Aug 03 04:32:04 PM PDT 24 Aug 03 04:32:05 PM PDT 24 61373432 ps
T42 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2595924700 Aug 03 04:31:32 PM PDT 24 Aug 03 04:31:33 PM PDT 24 17506977 ps
T43 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3554940525 Aug 03 04:31:41 PM PDT 24 Aug 03 04:31:42 PM PDT 24 43022390 ps
T71 /workspace/coverage/cover_reg_top/3.i2c_intr_test.388905839 Aug 03 04:31:20 PM PDT 24 Aug 03 04:31:20 PM PDT 24 19819080 ps
T50 /workspace/coverage/cover_reg_top/40.i2c_intr_test.4199101114 Aug 03 04:31:51 PM PDT 24 Aug 03 04:31:51 PM PDT 24 21516633 ps
T45 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3524445241 Aug 03 04:31:30 PM PDT 24 Aug 03 04:31:32 PM PDT 24 298417713 ps
T44 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.386957585 Aug 03 04:31:33 PM PDT 24 Aug 03 04:31:34 PM PDT 24 20728491 ps
T46 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3411081757 Aug 03 04:31:26 PM PDT 24 Aug 03 04:31:28 PM PDT 24 1477568144 ps
T86 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.722982400 Aug 03 04:31:22 PM PDT 24 Aug 03 04:31:23 PM PDT 24 136711864 ps
T67 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1722649608 Aug 03 04:31:15 PM PDT 24 Aug 03 04:31:15 PM PDT 24 31201458 ps
T47 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.419587538 Aug 03 04:31:32 PM PDT 24 Aug 03 04:31:34 PM PDT 24 447086454 ps
T58 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2900411066 Aug 03 04:31:33 PM PDT 24 Aug 03 04:31:36 PM PDT 24 88215408 ps
T72 /workspace/coverage/cover_reg_top/29.i2c_intr_test.525601734 Aug 03 04:31:48 PM PDT 24 Aug 03 04:31:49 PM PDT 24 14428765 ps
T51 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3538507213 Aug 03 04:31:10 PM PDT 24 Aug 03 04:31:11 PM PDT 24 50032461 ps
T87 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.248043594 Aug 03 04:31:29 PM PDT 24 Aug 03 04:31:32 PM PDT 24 530370595 ps
T27 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3263826487 Aug 03 04:31:19 PM PDT 24 Aug 03 04:31:21 PM PDT 24 40370068 ps
T55 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2452382475 Aug 03 04:31:26 PM PDT 24 Aug 03 04:31:29 PM PDT 24 134222415 ps
T84 /workspace/coverage/cover_reg_top/6.i2c_intr_test.636635441 Aug 03 04:31:21 PM PDT 24 Aug 03 04:31:22 PM PDT 24 93370977 ps
T88 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1469810883 Aug 03 04:31:32 PM PDT 24 Aug 03 04:31:33 PM PDT 24 83180106 ps
T89 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2788290114 Aug 03 04:31:32 PM PDT 24 Aug 03 04:31:33 PM PDT 24 76886532 ps
T68 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.895701933 Aug 03 04:31:41 PM PDT 24 Aug 03 04:31:42 PM PDT 24 190208431 ps
T74 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2832291255 Aug 03 04:31:39 PM PDT 24 Aug 03 04:31:40 PM PDT 24 18059809 ps
T82 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3608282033 Aug 03 04:31:52 PM PDT 24 Aug 03 04:31:53 PM PDT 24 47612561 ps
T90 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.561206327 Aug 03 04:31:34 PM PDT 24 Aug 03 04:31:36 PM PDT 24 161135697 ps
T91 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2339574757 Aug 03 04:31:41 PM PDT 24 Aug 03 04:31:42 PM PDT 24 42803761 ps
T92 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1649873545 Aug 03 04:31:31 PM PDT 24 Aug 03 04:31:31 PM PDT 24 53311759 ps
T93 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.762288469 Aug 03 04:31:42 PM PDT 24 Aug 03 04:31:43 PM PDT 24 73963483 ps
T28 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1598427884 Aug 03 04:31:21 PM PDT 24 Aug 03 04:31:22 PM PDT 24 22620583 ps
T94 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2743243470 Aug 03 04:31:26 PM PDT 24 Aug 03 04:31:27 PM PDT 24 39819353 ps
T73 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2764794151 Aug 03 04:31:46 PM PDT 24 Aug 03 04:31:47 PM PDT 24 35662201 ps
T75 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2468457398 Aug 03 04:31:48 PM PDT 24 Aug 03 04:31:49 PM PDT 24 49931474 ps
T95 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.71076784 Aug 03 04:31:24 PM PDT 24 Aug 03 04:31:27 PM PDT 24 45904089 ps
T83 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3896500944 Aug 03 04:31:47 PM PDT 24 Aug 03 04:31:48 PM PDT 24 17156250 ps
T33 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.420799701 Aug 03 04:31:28 PM PDT 24 Aug 03 04:31:29 PM PDT 24 69582022 ps
T96 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1152310737 Aug 03 04:31:53 PM PDT 24 Aug 03 04:31:53 PM PDT 24 19733898 ps
T29 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1867696441 Aug 03 04:31:11 PM PDT 24 Aug 03 04:31:14 PM PDT 24 65502729 ps
T76 /workspace/coverage/cover_reg_top/32.i2c_intr_test.3690875194 Aug 03 04:31:48 PM PDT 24 Aug 03 04:31:49 PM PDT 24 30834466 ps
T97 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3031599479 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:20 PM PDT 24 98192412 ps
T98 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2167614172 Aug 03 04:31:14 PM PDT 24 Aug 03 04:31:17 PM PDT 24 538348363 ps
T30 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2720569015 Aug 03 04:31:22 PM PDT 24 Aug 03 04:31:23 PM PDT 24 38484723 ps
T99 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3952037344 Aug 03 04:31:23 PM PDT 24 Aug 03 04:31:24 PM PDT 24 37330484 ps
T31 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.235937809 Aug 03 04:31:19 PM PDT 24 Aug 03 04:31:20 PM PDT 24 55965960 ps
T81 /workspace/coverage/cover_reg_top/36.i2c_intr_test.2495566845 Aug 03 04:31:50 PM PDT 24 Aug 03 04:31:51 PM PDT 24 57390618 ps
T66 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.376742077 Aug 03 04:31:26 PM PDT 24 Aug 03 04:31:28 PM PDT 24 56295578 ps
T60 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2801981322 Aug 03 04:31:30 PM PDT 24 Aug 03 04:31:32 PM PDT 24 55922143 ps
T61 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1803082861 Aug 03 04:31:20 PM PDT 24 Aug 03 04:31:22 PM PDT 24 50841035 ps
T100 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1647720260 Aug 03 04:31:26 PM PDT 24 Aug 03 04:31:27 PM PDT 24 52661535 ps
T101 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1409437949 Aug 03 04:31:33 PM PDT 24 Aug 03 04:31:35 PM PDT 24 302797145 ps
T48 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.592165546 Aug 03 04:31:30 PM PDT 24 Aug 03 04:31:31 PM PDT 24 43548454 ps
T102 /workspace/coverage/cover_reg_top/25.i2c_intr_test.2034177927 Aug 03 04:31:50 PM PDT 24 Aug 03 04:31:51 PM PDT 24 17450645 ps
T77 /workspace/coverage/cover_reg_top/46.i2c_intr_test.3203218786 Aug 03 04:31:49 PM PDT 24 Aug 03 04:31:50 PM PDT 24 34831796 ps
T32 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3672983784 Aug 03 04:31:24 PM PDT 24 Aug 03 04:31:25 PM PDT 24 80955704 ps
T49 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.8120256 Aug 03 04:31:38 PM PDT 24 Aug 03 04:31:39 PM PDT 24 41148898 ps
T103 /workspace/coverage/cover_reg_top/48.i2c_intr_test.141052986 Aug 03 04:31:49 PM PDT 24 Aug 03 04:31:50 PM PDT 24 18153209 ps
T104 /workspace/coverage/cover_reg_top/24.i2c_intr_test.1717748308 Aug 03 04:31:48 PM PDT 24 Aug 03 04:31:49 PM PDT 24 75822358 ps
T105 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2080668581 Aug 03 04:31:49 PM PDT 24 Aug 03 04:31:49 PM PDT 24 110060963 ps
T106 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3235579603 Aug 03 04:31:24 PM PDT 24 Aug 03 04:31:25 PM PDT 24 73650386 ps
T107 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2446266679 Aug 03 04:31:25 PM PDT 24 Aug 03 04:31:26 PM PDT 24 154867216 ps
T108 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1686672662 Aug 03 04:31:26 PM PDT 24 Aug 03 04:31:28 PM PDT 24 321040319 ps
T69 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3228976662 Aug 03 04:31:43 PM PDT 24 Aug 03 04:31:45 PM PDT 24 97235138 ps
T109 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.4161980252 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:19 PM PDT 24 16774728 ps
T110 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4238272210 Aug 03 04:31:39 PM PDT 24 Aug 03 04:31:40 PM PDT 24 123287265 ps
T111 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.130550948 Aug 03 04:31:11 PM PDT 24 Aug 03 04:31:14 PM PDT 24 485333163 ps
T34 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3656055395 Aug 03 04:31:15 PM PDT 24 Aug 03 04:31:17 PM PDT 24 41841603 ps
T112 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2549296186 Aug 03 04:31:20 PM PDT 24 Aug 03 04:31:21 PM PDT 24 17288301 ps
T35 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3141980918 Aug 03 04:31:13 PM PDT 24 Aug 03 04:31:14 PM PDT 24 60616544 ps
T113 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2095000851 Aug 03 04:31:28 PM PDT 24 Aug 03 04:31:31 PM PDT 24 291976004 ps
T114 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3370380878 Aug 03 04:31:26 PM PDT 24 Aug 03 04:31:27 PM PDT 24 24996067 ps
T115 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3823285488 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:20 PM PDT 24 401834225 ps
T116 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3955772327 Aug 03 04:31:17 PM PDT 24 Aug 03 04:31:18 PM PDT 24 265266994 ps
T78 /workspace/coverage/cover_reg_top/38.i2c_intr_test.638310959 Aug 03 04:31:46 PM PDT 24 Aug 03 04:31:47 PM PDT 24 20359737 ps
T117 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.854298946 Aug 03 04:31:20 PM PDT 24 Aug 03 04:31:21 PM PDT 24 37235509 ps
T36 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1652353092 Aug 03 04:31:30 PM PDT 24 Aug 03 04:31:31 PM PDT 24 19565207 ps
T52 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.159575580 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:20 PM PDT 24 24953930 ps
T85 /workspace/coverage/cover_reg_top/37.i2c_intr_test.2455857999 Aug 03 04:31:47 PM PDT 24 Aug 03 04:31:48 PM PDT 24 31010229 ps
T118 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3897655257 Aug 03 04:31:28 PM PDT 24 Aug 03 04:31:29 PM PDT 24 29143005 ps
T119 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1159331196 Aug 03 04:31:11 PM PDT 24 Aug 03 04:31:12 PM PDT 24 26033990 ps
T120 /workspace/coverage/cover_reg_top/43.i2c_intr_test.3957199592 Aug 03 04:31:48 PM PDT 24 Aug 03 04:31:49 PM PDT 24 16079650 ps
T79 /workspace/coverage/cover_reg_top/8.i2c_intr_test.323924484 Aug 03 04:31:25 PM PDT 24 Aug 03 04:31:26 PM PDT 24 86321416 ps
T121 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1770236275 Aug 03 04:31:48 PM PDT 24 Aug 03 04:31:49 PM PDT 24 60780809 ps
T122 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.558604582 Aug 03 04:31:24 PM PDT 24 Aug 03 04:31:25 PM PDT 24 47414677 ps
T57 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2056753326 Aug 03 04:31:25 PM PDT 24 Aug 03 04:31:27 PM PDT 24 121886006 ps
T123 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.855923025 Aug 03 04:31:34 PM PDT 24 Aug 03 04:31:35 PM PDT 24 26406115 ps
T64 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1568916353 Aug 03 04:31:29 PM PDT 24 Aug 03 04:31:31 PM PDT 24 81198822 ps
T124 /workspace/coverage/cover_reg_top/7.i2c_intr_test.524518377 Aug 03 04:31:30 PM PDT 24 Aug 03 04:31:31 PM PDT 24 25433765 ps
T125 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.291010683 Aug 03 04:31:26 PM PDT 24 Aug 03 04:31:27 PM PDT 24 43324267 ps
T53 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2868266067 Aug 03 04:31:32 PM PDT 24 Aug 03 04:31:34 PM PDT 24 801518350 ps
T56 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2700317683 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:20 PM PDT 24 274091701 ps
T126 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3340311997 Aug 03 04:31:14 PM PDT 24 Aug 03 04:31:15 PM PDT 24 98136933 ps
T127 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3664744296 Aug 03 04:31:49 PM PDT 24 Aug 03 04:31:50 PM PDT 24 18616523 ps
T128 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.794083759 Aug 03 04:31:13 PM PDT 24 Aug 03 04:31:14 PM PDT 24 157205064 ps
T129 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3835552453 Aug 03 04:31:31 PM PDT 24 Aug 03 04:31:32 PM PDT 24 63308305 ps
T130 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2839529427 Aug 03 04:31:27 PM PDT 24 Aug 03 04:31:30 PM PDT 24 185445601 ps
T131 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3819343291 Aug 03 04:31:40 PM PDT 24 Aug 03 04:31:42 PM PDT 24 27376474 ps
T132 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1004060920 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:19 PM PDT 24 72601396 ps
T80 /workspace/coverage/cover_reg_top/9.i2c_intr_test.4151677316 Aug 03 04:32:01 PM PDT 24 Aug 03 04:32:02 PM PDT 24 19416527 ps
T133 /workspace/coverage/cover_reg_top/4.i2c_intr_test.70835033 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:19 PM PDT 24 17137578 ps
T134 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1956280380 Aug 03 04:31:33 PM PDT 24 Aug 03 04:31:34 PM PDT 24 16382979 ps
T135 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2388068817 Aug 03 04:31:28 PM PDT 24 Aug 03 04:31:29 PM PDT 24 61182448 ps
T136 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2335819631 Aug 03 04:31:19 PM PDT 24 Aug 03 04:31:22 PM PDT 24 743120081 ps
T137 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3472338424 Aug 03 04:31:11 PM PDT 24 Aug 03 04:31:12 PM PDT 24 24423193 ps
T37 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1040235667 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:23 PM PDT 24 117915187 ps
T138 /workspace/coverage/cover_reg_top/19.i2c_intr_test.2566318331 Aug 03 04:31:38 PM PDT 24 Aug 03 04:31:39 PM PDT 24 20308354 ps
T139 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1437367166 Aug 03 04:31:51 PM PDT 24 Aug 03 04:31:51 PM PDT 24 17373088 ps
T59 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1329270254 Aug 03 04:31:27 PM PDT 24 Aug 03 04:31:28 PM PDT 24 151165079 ps
T140 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2538756341 Aug 03 04:31:34 PM PDT 24 Aug 03 04:31:36 PM PDT 24 1657352337 ps
T141 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2376485591 Aug 03 04:31:26 PM PDT 24 Aug 03 04:31:26 PM PDT 24 54563878 ps
T142 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3834646851 Aug 03 04:31:27 PM PDT 24 Aug 03 04:31:28 PM PDT 24 70592491 ps
T38 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3745021410 Aug 03 04:31:21 PM PDT 24 Aug 03 04:31:23 PM PDT 24 1033290152 ps
T143 /workspace/coverage/cover_reg_top/5.i2c_intr_test.1397369881 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:19 PM PDT 24 16411234 ps
T144 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2717714388 Aug 03 04:31:23 PM PDT 24 Aug 03 04:31:25 PM PDT 24 45076788 ps
T145 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1998716196 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:21 PM PDT 24 82236063 ps
T146 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2631593452 Aug 03 04:31:28 PM PDT 24 Aug 03 04:31:29 PM PDT 24 18318280 ps
T147 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2007757023 Aug 03 04:31:20 PM PDT 24 Aug 03 04:31:21 PM PDT 24 823711034 ps
T148 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1299436852 Aug 03 04:31:48 PM PDT 24 Aug 03 04:31:49 PM PDT 24 26319240 ps
T65 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.463284432 Aug 03 04:31:17 PM PDT 24 Aug 03 04:31:19 PM PDT 24 83060627 ps
T63 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1878979820 Aug 03 04:31:20 PM PDT 24 Aug 03 04:31:22 PM PDT 24 94693865 ps
T149 /workspace/coverage/cover_reg_top/10.i2c_intr_test.4162883815 Aug 03 04:31:23 PM PDT 24 Aug 03 04:31:24 PM PDT 24 15958831 ps
T150 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3991386193 Aug 03 04:31:25 PM PDT 24 Aug 03 04:31:26 PM PDT 24 80882385 ps
T151 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2972690852 Aug 03 04:31:31 PM PDT 24 Aug 03 04:31:32 PM PDT 24 52502083 ps
T152 /workspace/coverage/cover_reg_top/30.i2c_intr_test.794056292 Aug 03 04:31:52 PM PDT 24 Aug 03 04:31:52 PM PDT 24 16857583 ps
T39 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3869472131 Aug 03 04:31:18 PM PDT 24 Aug 03 04:31:19 PM PDT 24 70334539 ps
T62 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2279502825 Aug 03 04:31:28 PM PDT 24 Aug 03 04:31:30 PM PDT 24 174580950 ps
T153 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.360983717 Aug 03 04:31:27 PM PDT 24 Aug 03 04:31:29 PM PDT 24 110865301 ps
T154 /workspace/coverage/cover_reg_top/35.i2c_intr_test.303450550 Aug 03 04:31:52 PM PDT 24 Aug 03 04:31:53 PM PDT 24 22433228 ps
T155 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2666769686 Aug 03 04:31:19 PM PDT 24 Aug 03 04:31:20 PM PDT 24 19687867 ps
T156 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3346860670 Aug 03 04:31:39 PM PDT 24 Aug 03 04:31:40 PM PDT 24 15902156 ps
T157 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.880347994 Aug 03 04:31:33 PM PDT 24 Aug 03 04:31:34 PM PDT 24 212176579 ps
T158 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3549548903 Aug 03 04:31:27 PM PDT 24 Aug 03 04:31:28 PM PDT 24 19119273 ps
T159 /workspace/coverage/cover_reg_top/18.i2c_intr_test.4165033638 Aug 03 04:31:39 PM PDT 24 Aug 03 04:31:40 PM PDT 24 24733642 ps
T160 /workspace/coverage/cover_reg_top/27.i2c_intr_test.1143682404 Aug 03 04:31:47 PM PDT 24 Aug 03 04:31:48 PM PDT 24 86228243 ps
T161 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.898645466 Aug 03 04:31:25 PM PDT 24 Aug 03 04:31:27 PM PDT 24 524701513 ps
T162 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3884641787 Aug 03 04:31:19 PM PDT 24 Aug 03 04:31:21 PM PDT 24 166532113 ps
T163 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1630858648 Aug 03 04:31:20 PM PDT 24 Aug 03 04:31:21 PM PDT 24 20784069 ps
T40 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3822192490 Aug 03 04:31:19 PM PDT 24 Aug 03 04:31:20 PM PDT 24 26530376 ps
T164 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3374426575 Aug 03 04:31:17 PM PDT 24 Aug 03 04:31:23 PM PDT 24 2139289266 ps
T165 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.752829179 Aug 03 04:31:25 PM PDT 24 Aug 03 04:31:26 PM PDT 24 81376303 ps

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.212008960
Short name T4
Test name
Test status
Simulation time 180918578 ps
CPU time 1.07 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:19 PM PDT 24
Peak memory 204568 kb
Host smart-1b0f94ae-5340-48ab-b748-a04cf7965eca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212008960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.212008960
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.4040154049
Short name T1
Test name
Test status
Simulation time 26735505 ps
CPU time 0.7 seconds
Started Aug 03 04:31:40 PM PDT 24
Finished Aug 03 04:31:41 PM PDT 24
Peak memory 204236 kb
Host smart-2d6de503-0da4-445c-a4da-49c2e38d9bbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040154049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.4040154049
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.738853683
Short name T3
Test name
Test status
Simulation time 112493672 ps
CPU time 2.52 seconds
Started Aug 03 04:31:13 PM PDT 24
Finished Aug 03 04:31:16 PM PDT 24
Peak memory 212704 kb
Host smart-086c2c65-5fe0-4c3e-a9cf-83f94451ba26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738853683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.738853683
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.829452243
Short name T25
Test name
Test status
Simulation time 19485687 ps
CPU time 0.79 seconds
Started Aug 03 04:31:23 PM PDT 24
Finished Aug 03 04:31:23 PM PDT 24
Peak memory 204280 kb
Host smart-954d2225-9075-4cbd-b04a-df809ccdda15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829452243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.829452243
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.116888270
Short name T12
Test name
Test status
Simulation time 24587400 ps
CPU time 0.68 seconds
Started Aug 03 04:31:48 PM PDT 24
Finished Aug 03 04:31:49 PM PDT 24
Peak memory 204176 kb
Host smart-c55603f8-571d-4e5e-9e78-e86e6f3118b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116888270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.116888270
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.419587538
Short name T47
Test name
Test status
Simulation time 447086454 ps
CPU time 2.31 seconds
Started Aug 03 04:31:32 PM PDT 24
Finished Aug 03 04:31:34 PM PDT 24
Peak memory 204360 kb
Host smart-4701a4cc-ba66-43a5-9cb0-d5107f305ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419587538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.419587538
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3538507213
Short name T51
Test name
Test status
Simulation time 50032461 ps
CPU time 0.64 seconds
Started Aug 03 04:31:10 PM PDT 24
Finished Aug 03 04:31:11 PM PDT 24
Peak memory 204180 kb
Host smart-d16dc6d7-b3ef-4c00-84c9-10d33fb0a971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538507213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3538507213
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3141980918
Short name T35
Test name
Test status
Simulation time 60616544 ps
CPU time 0.76 seconds
Started Aug 03 04:31:13 PM PDT 24
Finished Aug 03 04:31:14 PM PDT 24
Peak memory 204304 kb
Host smart-7eede4b7-bc32-4492-afcb-85ec42b394e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141980918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3141980918
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.388905839
Short name T71
Test name
Test status
Simulation time 19819080 ps
CPU time 0.68 seconds
Started Aug 03 04:31:20 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204136 kb
Host smart-d95409a7-6c96-404a-94a2-1032d235b5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388905839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.388905839
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.592165546
Short name T48
Test name
Test status
Simulation time 43548454 ps
CPU time 0.91 seconds
Started Aug 03 04:31:30 PM PDT 24
Finished Aug 03 04:31:31 PM PDT 24
Peak memory 204336 kb
Host smart-44acf5f7-6860-4cfd-962d-4da87f99f146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592165546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou
tstanding.592165546
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2452382475
Short name T55
Test name
Test status
Simulation time 134222415 ps
CPU time 2.07 seconds
Started Aug 03 04:31:26 PM PDT 24
Finished Aug 03 04:31:29 PM PDT 24
Peak memory 204408 kb
Host smart-37f02967-5387-4e01-926c-1caa8ee9400d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452382475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2452382475
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2684315665
Short name T24
Test name
Test status
Simulation time 19566576 ps
CPU time 0.79 seconds
Started Aug 03 04:31:13 PM PDT 24
Finished Aug 03 04:31:14 PM PDT 24
Peak memory 204428 kb
Host smart-ab4a40a9-2e9c-4af1-9743-233a804631cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684315665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2684315665
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.376742077
Short name T66
Test name
Test status
Simulation time 56295578 ps
CPU time 0.86 seconds
Started Aug 03 04:31:26 PM PDT 24
Finished Aug 03 04:31:28 PM PDT 24
Peak memory 203568 kb
Host smart-f9a82c95-93c8-4ded-a0e6-1fecfb0ad92d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376742077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.376742077
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2972690852
Short name T151
Test name
Test status
Simulation time 52502083 ps
CPU time 0.69 seconds
Started Aug 03 04:31:31 PM PDT 24
Finished Aug 03 04:31:32 PM PDT 24
Peak memory 204136 kb
Host smart-d134df0b-ba72-4514-b8d3-373464d5fcbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972690852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2972690852
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1469810883
Short name T88
Test name
Test status
Simulation time 83180106 ps
CPU time 1.22 seconds
Started Aug 03 04:31:32 PM PDT 24
Finished Aug 03 04:31:33 PM PDT 24
Peak memory 204472 kb
Host smart-91923545-889c-4e72-8734-7fb32f2a2fed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469810883 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1469810883
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2056753326
Short name T57
Test name
Test status
Simulation time 121886006 ps
CPU time 2.29 seconds
Started Aug 03 04:31:25 PM PDT 24
Finished Aug 03 04:31:27 PM PDT 24
Peak memory 204428 kb
Host smart-ad9e79f6-0c06-45fa-acdb-593ff17e23d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056753326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2056753326
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1568916353
Short name T64
Test name
Test status
Simulation time 81198822 ps
CPU time 2.11 seconds
Started Aug 03 04:31:29 PM PDT 24
Finished Aug 03 04:31:31 PM PDT 24
Peak memory 204388 kb
Host smart-1e0af27f-652b-4da4-8666-a5838d6c21d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568916353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1568916353
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2801981322
Short name T60
Test name
Test status
Simulation time 55922143 ps
CPU time 1.32 seconds
Started Aug 03 04:31:30 PM PDT 24
Finished Aug 03 04:31:32 PM PDT 24
Peak memory 204424 kb
Host smart-fa7d78fd-b2a5-48e4-9feb-1f3b29adf5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801981322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2801981322
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3656055395
Short name T34
Test name
Test status
Simulation time 41841603 ps
CPU time 1.81 seconds
Started Aug 03 04:31:15 PM PDT 24
Finished Aug 03 04:31:17 PM PDT 24
Peak memory 204404 kb
Host smart-119366b0-f7c7-427f-8405-cf3b78519d0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656055395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3656055395
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1867696441
Short name T29
Test name
Test status
Simulation time 65502729 ps
CPU time 2.61 seconds
Started Aug 03 04:31:11 PM PDT 24
Finished Aug 03 04:31:14 PM PDT 24
Peak memory 204432 kb
Host smart-77cf6f7a-56af-4b38-9823-72e0e577b8cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867696441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1867696441
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.485821127
Short name T6
Test name
Test status
Simulation time 124052237 ps
CPU time 0.76 seconds
Started Aug 03 04:31:11 PM PDT 24
Finished Aug 03 04:31:12 PM PDT 24
Peak memory 204312 kb
Host smart-c14bfac9-9185-44d3-989b-b0667de51626
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485821127 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.485821127
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3955772327
Short name T116
Test name
Test status
Simulation time 265266994 ps
CPU time 1.16 seconds
Started Aug 03 04:31:17 PM PDT 24
Finished Aug 03 04:31:18 PM PDT 24
Peak memory 204500 kb
Host smart-9e3ad991-642c-4077-99de-710d8a8d1572
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955772327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.3955772327
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3884641787
Short name T162
Test name
Test status
Simulation time 166532113 ps
CPU time 2.05 seconds
Started Aug 03 04:31:19 PM PDT 24
Finished Aug 03 04:31:21 PM PDT 24
Peak memory 204300 kb
Host smart-e8c7fc67-59b9-4f84-b4f1-3e10ef3d7f83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884641787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3884641787
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1019537569
Short name T9
Test name
Test status
Simulation time 191837926 ps
CPU time 1.92 seconds
Started Aug 03 04:31:20 PM PDT 24
Finished Aug 03 04:31:22 PM PDT 24
Peak memory 204452 kb
Host smart-fa87a6b5-cfa9-4a10-b3cc-9dee3eff5c98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019537569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1019537569
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.130550948
Short name T111
Test name
Test status
Simulation time 485333163 ps
CPU time 2.9 seconds
Started Aug 03 04:31:11 PM PDT 24
Finished Aug 03 04:31:14 PM PDT 24
Peak memory 204400 kb
Host smart-2f96b2b8-1d04-4a2b-b7ae-63feab882397
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130550948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.130550948
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3869472131
Short name T39
Test name
Test status
Simulation time 70334539 ps
CPU time 0.79 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:19 PM PDT 24
Peak memory 204252 kb
Host smart-60142b4b-a828-4187-b6c3-eeb8f9a70459
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869472131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3869472131
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1159331196
Short name T119
Test name
Test status
Simulation time 26033990 ps
CPU time 0.8 seconds
Started Aug 03 04:31:11 PM PDT 24
Finished Aug 03 04:31:12 PM PDT 24
Peak memory 204392 kb
Host smart-eedf8115-f8dd-47be-a131-36943cdc5192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159331196 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1159331196
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1598427884
Short name T28
Test name
Test status
Simulation time 22620583 ps
CPU time 0.71 seconds
Started Aug 03 04:31:21 PM PDT 24
Finished Aug 03 04:31:22 PM PDT 24
Peak memory 204288 kb
Host smart-844ace06-27ae-4f88-a3ec-3dbb44228f90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598427884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1598427884
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3472338424
Short name T137
Test name
Test status
Simulation time 24423193 ps
CPU time 0.68 seconds
Started Aug 03 04:31:11 PM PDT 24
Finished Aug 03 04:31:12 PM PDT 24
Peak memory 204192 kb
Host smart-39a2e15d-0281-49af-8a7c-dfaa1f400696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472338424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3472338424
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1722649608
Short name T67
Test name
Test status
Simulation time 31201458 ps
CPU time 0.82 seconds
Started Aug 03 04:31:15 PM PDT 24
Finished Aug 03 04:31:15 PM PDT 24
Peak memory 204340 kb
Host smart-0df64f41-e4a7-4f7e-9847-c47eaf37bef5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722649608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1722649608
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3823285488
Short name T115
Test name
Test status
Simulation time 401834225 ps
CPU time 1.6 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204820 kb
Host smart-9c4902e2-894a-41fd-b3dc-c432f09e1974
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823285488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3823285488
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.794083759
Short name T128
Test name
Test status
Simulation time 157205064 ps
CPU time 1.42 seconds
Started Aug 03 04:31:13 PM PDT 24
Finished Aug 03 04:31:14 PM PDT 24
Peak memory 204424 kb
Host smart-552712ae-b1c2-4e25-95e4-02308c74b9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794083759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.794083759
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1409437949
Short name T101
Test name
Test status
Simulation time 302797145 ps
CPU time 1.12 seconds
Started Aug 03 04:31:33 PM PDT 24
Finished Aug 03 04:31:35 PM PDT 24
Peak memory 204460 kb
Host smart-40bf595e-c3c6-4481-bbe5-a7cd5a916e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409437949 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1409437949
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2376485591
Short name T141
Test name
Test status
Simulation time 54563878 ps
CPU time 0.67 seconds
Started Aug 03 04:31:26 PM PDT 24
Finished Aug 03 04:31:26 PM PDT 24
Peak memory 204260 kb
Host smart-802ed060-ebdf-4b94-8336-e96342cd339e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376485591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2376485591
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.4162883815
Short name T149
Test name
Test status
Simulation time 15958831 ps
CPU time 0.68 seconds
Started Aug 03 04:31:23 PM PDT 24
Finished Aug 03 04:31:24 PM PDT 24
Peak memory 204128 kb
Host smart-958e925b-baac-42e3-9064-9a97e7cd26da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162883815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.4162883815
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3595112076
Short name T16
Test name
Test status
Simulation time 294741696 ps
CPU time 1.9 seconds
Started Aug 03 04:31:25 PM PDT 24
Finished Aug 03 04:31:28 PM PDT 24
Peak memory 204512 kb
Host smart-f4d417d4-3b7a-42ef-90cd-9f32e39fa57a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595112076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3595112076
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1329270254
Short name T59
Test name
Test status
Simulation time 151165079 ps
CPU time 1.37 seconds
Started Aug 03 04:31:27 PM PDT 24
Finished Aug 03 04:31:28 PM PDT 24
Peak memory 204388 kb
Host smart-c7e7fee9-aa9a-4767-8e4e-ddd260a370dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329270254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1329270254
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3235579603
Short name T106
Test name
Test status
Simulation time 73650386 ps
CPU time 0.79 seconds
Started Aug 03 04:31:24 PM PDT 24
Finished Aug 03 04:31:25 PM PDT 24
Peak memory 204368 kb
Host smart-3b3c3674-8191-4b07-b2e9-2ebd9a82a8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235579603 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3235579603
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.558604582
Short name T122
Test name
Test status
Simulation time 47414677 ps
CPU time 0.65 seconds
Started Aug 03 04:31:24 PM PDT 24
Finished Aug 03 04:31:25 PM PDT 24
Peak memory 204384 kb
Host smart-60ba38bf-5074-457c-baa2-9c6e4a6a86e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558604582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.558604582
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3549548903
Short name T158
Test name
Test status
Simulation time 19119273 ps
CPU time 0.66 seconds
Started Aug 03 04:31:27 PM PDT 24
Finished Aug 03 04:31:28 PM PDT 24
Peak memory 204244 kb
Host smart-24f512d6-39fd-4bc5-9b60-24c71d46e5fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549548903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3549548903
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.276245629
Short name T10
Test name
Test status
Simulation time 171331808 ps
CPU time 1.09 seconds
Started Aug 03 04:31:25 PM PDT 24
Finished Aug 03 04:31:26 PM PDT 24
Peak memory 204368 kb
Host smart-142ef833-8aad-47a4-b7ee-0f94287c5463
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276245629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou
tstanding.276245629
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2095000851
Short name T113
Test name
Test status
Simulation time 291976004 ps
CPU time 2.2 seconds
Started Aug 03 04:31:28 PM PDT 24
Finished Aug 03 04:31:31 PM PDT 24
Peak memory 212640 kb
Host smart-09c0c9fa-2ffb-4f0f-b026-dba6682a981c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095000851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2095000851
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3370380878
Short name T114
Test name
Test status
Simulation time 24996067 ps
CPU time 0.8 seconds
Started Aug 03 04:31:26 PM PDT 24
Finished Aug 03 04:31:27 PM PDT 24
Peak memory 204480 kb
Host smart-ac741c6d-6fde-49f5-8656-31be05d2affc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370380878 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3370380878
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2743243470
Short name T94
Test name
Test status
Simulation time 39819353 ps
CPU time 0.78 seconds
Started Aug 03 04:31:26 PM PDT 24
Finished Aug 03 04:31:27 PM PDT 24
Peak memory 204320 kb
Host smart-f02c2a12-1085-43f2-9f64-fb4cb044d46a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743243470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2743243470
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2631593452
Short name T146
Test name
Test status
Simulation time 18318280 ps
CPU time 0.66 seconds
Started Aug 03 04:31:28 PM PDT 24
Finished Aug 03 04:31:29 PM PDT 24
Peak memory 204192 kb
Host smart-334d2ad3-fe56-4435-88b0-9e910b417959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631593452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2631593452
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1647720260
Short name T100
Test name
Test status
Simulation time 52661535 ps
CPU time 1.12 seconds
Started Aug 03 04:31:26 PM PDT 24
Finished Aug 03 04:31:27 PM PDT 24
Peak memory 204620 kb
Host smart-e507dc33-3a60-4b7c-b8f8-7b98811320dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647720260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.1647720260
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1686672662
Short name T108
Test name
Test status
Simulation time 321040319 ps
CPU time 1.82 seconds
Started Aug 03 04:31:26 PM PDT 24
Finished Aug 03 04:31:28 PM PDT 24
Peak memory 203972 kb
Host smart-88c50a31-6d2e-4ce0-bfe6-da2ab10c5e26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686672662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1686672662
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3802292155
Short name T18
Test name
Test status
Simulation time 119055336 ps
CPU time 0.93 seconds
Started Aug 03 04:31:33 PM PDT 24
Finished Aug 03 04:31:34 PM PDT 24
Peak memory 204008 kb
Host smart-cefd6c04-f5e2-4662-8f18-4811f136ac19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802292155 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3802292155
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.420799701
Short name T33
Test name
Test status
Simulation time 69582022 ps
CPU time 0.68 seconds
Started Aug 03 04:31:28 PM PDT 24
Finished Aug 03 04:31:29 PM PDT 24
Peak memory 204252 kb
Host smart-019bc40a-3c91-442a-8f8b-4a50d8d26b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420799701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.420799701
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3480060775
Short name T21
Test name
Test status
Simulation time 17777126 ps
CPU time 0.67 seconds
Started Aug 03 04:31:25 PM PDT 24
Finished Aug 03 04:31:26 PM PDT 24
Peak memory 204320 kb
Host smart-d1dc4387-a825-4d35-b7b6-14066adeee33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480060775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3480060775
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2388068817
Short name T135
Test name
Test status
Simulation time 61182448 ps
CPU time 0.89 seconds
Started Aug 03 04:31:28 PM PDT 24
Finished Aug 03 04:31:29 PM PDT 24
Peak memory 204328 kb
Host smart-880d7843-e8b5-49a4-80ad-d70e8490647e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388068817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.2388068817
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3411081757
Short name T46
Test name
Test status
Simulation time 1477568144 ps
CPU time 1.72 seconds
Started Aug 03 04:31:26 PM PDT 24
Finished Aug 03 04:31:28 PM PDT 24
Peak memory 204444 kb
Host smart-f6e8f134-09d6-4daa-8ace-a578966a8c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411081757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3411081757
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4235257366
Short name T54
Test name
Test status
Simulation time 139850204 ps
CPU time 1.36 seconds
Started Aug 03 04:31:29 PM PDT 24
Finished Aug 03 04:31:31 PM PDT 24
Peak memory 204364 kb
Host smart-76474964-d536-4737-8593-96856a73d269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235257366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.4235257366
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3991386193
Short name T150
Test name
Test status
Simulation time 80882385 ps
CPU time 0.67 seconds
Started Aug 03 04:31:25 PM PDT 24
Finished Aug 03 04:31:26 PM PDT 24
Peak memory 204204 kb
Host smart-c56c8e47-0160-4071-8e9f-99c40a43ee9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991386193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3991386193
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3897655257
Short name T118
Test name
Test status
Simulation time 29143005 ps
CPU time 0.65 seconds
Started Aug 03 04:31:28 PM PDT 24
Finished Aug 03 04:31:29 PM PDT 24
Peak memory 204232 kb
Host smart-c5e16ff6-6a7d-4669-bca0-2de2f6149ab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897655257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3897655257
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2900411066
Short name T58
Test name
Test status
Simulation time 88215408 ps
CPU time 2.41 seconds
Started Aug 03 04:31:33 PM PDT 24
Finished Aug 03 04:31:36 PM PDT 24
Peak memory 204488 kb
Host smart-c177b6c4-64ca-4dd2-b987-a722d2f8e36f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900411066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2900411066
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.422544994
Short name T17
Test name
Test status
Simulation time 255538441 ps
CPU time 0.78 seconds
Started Aug 03 04:31:34 PM PDT 24
Finished Aug 03 04:31:35 PM PDT 24
Peak memory 204328 kb
Host smart-a492ccd6-7fff-4c9f-bfd5-002b9a107b12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422544994 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.422544994
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2595924700
Short name T42
Test name
Test status
Simulation time 17506977 ps
CPU time 0.73 seconds
Started Aug 03 04:31:32 PM PDT 24
Finished Aug 03 04:31:33 PM PDT 24
Peak memory 204340 kb
Host smart-e0fe6e9f-da40-4f3b-81cf-ce4149dc1b17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595924700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2595924700
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3289670807
Short name T70
Test name
Test status
Simulation time 17979140 ps
CPU time 0.63 seconds
Started Aug 03 04:31:31 PM PDT 24
Finished Aug 03 04:31:32 PM PDT 24
Peak memory 204204 kb
Host smart-1640c684-2cab-4bc9-8e92-6beaca1be0a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289670807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3289670807
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1986445576
Short name T5
Test name
Test status
Simulation time 252116100 ps
CPU time 1.16 seconds
Started Aug 03 04:31:32 PM PDT 24
Finished Aug 03 04:31:34 PM PDT 24
Peak memory 204440 kb
Host smart-8839a86f-956d-45b7-8eee-73388f7b82ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986445576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.1986445576
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2538756341
Short name T140
Test name
Test status
Simulation time 1657352337 ps
CPU time 2.37 seconds
Started Aug 03 04:31:34 PM PDT 24
Finished Aug 03 04:31:36 PM PDT 24
Peak memory 204460 kb
Host smart-b5c63a34-bf8b-4f56-a561-e3db0b5a3164
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538756341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2538756341
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2788290114
Short name T89
Test name
Test status
Simulation time 76886532 ps
CPU time 1.04 seconds
Started Aug 03 04:31:32 PM PDT 24
Finished Aug 03 04:31:33 PM PDT 24
Peak memory 212728 kb
Host smart-f0ff244b-9f67-427c-8e33-da14466a2145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788290114 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2788290114
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1348268203
Short name T26
Test name
Test status
Simulation time 26860518 ps
CPU time 0.76 seconds
Started Aug 03 04:31:34 PM PDT 24
Finished Aug 03 04:31:35 PM PDT 24
Peak memory 204276 kb
Host smart-747807a4-c3aa-47fb-bd90-3d4e3fda858c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348268203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1348268203
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3835552453
Short name T129
Test name
Test status
Simulation time 63308305 ps
CPU time 0.88 seconds
Started Aug 03 04:31:31 PM PDT 24
Finished Aug 03 04:31:32 PM PDT 24
Peak memory 204308 kb
Host smart-4433d576-b4a6-4e01-bfcf-8e85719eb947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835552453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3835552453
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.248043594
Short name T87
Test name
Test status
Simulation time 530370595 ps
CPU time 2.3 seconds
Started Aug 03 04:31:29 PM PDT 24
Finished Aug 03 04:31:32 PM PDT 24
Peak memory 204432 kb
Host smart-5c521d56-b7ed-4419-bd70-012f8fa82b49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248043594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.248043594
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2868266067
Short name T53
Test name
Test status
Simulation time 801518350 ps
CPU time 2.38 seconds
Started Aug 03 04:31:32 PM PDT 24
Finished Aug 03 04:31:34 PM PDT 24
Peak memory 203880 kb
Host smart-df3dfeda-fbd6-4861-91b8-6a2053a1293a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868266067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2868266067
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.855923025
Short name T123
Test name
Test status
Simulation time 26406115 ps
CPU time 0.81 seconds
Started Aug 03 04:31:34 PM PDT 24
Finished Aug 03 04:31:35 PM PDT 24
Peak memory 204348 kb
Host smart-bba46cb4-cd09-4ebe-afdc-e08d5cf11607
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855923025 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.855923025
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1652353092
Short name T36
Test name
Test status
Simulation time 19565207 ps
CPU time 0.73 seconds
Started Aug 03 04:31:30 PM PDT 24
Finished Aug 03 04:31:31 PM PDT 24
Peak memory 204388 kb
Host smart-10ad3ac4-e28f-4b93-9524-d759a50744eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652353092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1652353092
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1956280380
Short name T134
Test name
Test status
Simulation time 16382979 ps
CPU time 0.66 seconds
Started Aug 03 04:31:33 PM PDT 24
Finished Aug 03 04:31:34 PM PDT 24
Peak memory 204184 kb
Host smart-e78ea993-daf1-468c-9198-cf1c9ef50f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956280380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1956280380
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1649873545
Short name T92
Test name
Test status
Simulation time 53311759 ps
CPU time 0.83 seconds
Started Aug 03 04:31:31 PM PDT 24
Finished Aug 03 04:31:31 PM PDT 24
Peak memory 204276 kb
Host smart-3cdc1a3e-c8fe-47f8-af7b-1595e40d335d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649873545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1649873545
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.561206327
Short name T90
Test name
Test status
Simulation time 161135697 ps
CPU time 1.98 seconds
Started Aug 03 04:31:34 PM PDT 24
Finished Aug 03 04:31:36 PM PDT 24
Peak memory 204512 kb
Host smart-49372cdc-f193-45db-a555-5835bfaa53a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561206327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.561206327
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3524445241
Short name T45
Test name
Test status
Simulation time 298417713 ps
CPU time 1.48 seconds
Started Aug 03 04:31:30 PM PDT 24
Finished Aug 03 04:31:32 PM PDT 24
Peak memory 204436 kb
Host smart-ae0c021b-ea34-4830-8005-a25e0f260bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524445241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3524445241
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2339574757
Short name T91
Test name
Test status
Simulation time 42803761 ps
CPU time 0.79 seconds
Started Aug 03 04:31:41 PM PDT 24
Finished Aug 03 04:31:42 PM PDT 24
Peak memory 204388 kb
Host smart-20192254-52f6-4031-aba5-121fafe438ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339574757 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2339574757
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3554940525
Short name T43
Test name
Test status
Simulation time 43022390 ps
CPU time 0.67 seconds
Started Aug 03 04:31:41 PM PDT 24
Finished Aug 03 04:31:42 PM PDT 24
Peak memory 204264 kb
Host smart-352238f7-0e43-4c78-8a7d-f437bf61d26c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554940525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3554940525
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.4165033638
Short name T159
Test name
Test status
Simulation time 24733642 ps
CPU time 0.64 seconds
Started Aug 03 04:31:39 PM PDT 24
Finished Aug 03 04:31:40 PM PDT 24
Peak memory 204196 kb
Host smart-6f0a321d-3d7f-46b2-b1fa-d902325e7941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165033638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.4165033638
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4238272210
Short name T110
Test name
Test status
Simulation time 123287265 ps
CPU time 0.85 seconds
Started Aug 03 04:31:39 PM PDT 24
Finished Aug 03 04:31:40 PM PDT 24
Peak memory 204328 kb
Host smart-aaa968e9-75c0-49a2-bf9d-d4643d628d3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238272210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.4238272210
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3943605203
Short name T13
Test name
Test status
Simulation time 45046407 ps
CPU time 2.3 seconds
Started Aug 03 04:31:31 PM PDT 24
Finished Aug 03 04:31:34 PM PDT 24
Peak memory 204488 kb
Host smart-53fc91b8-e53d-4859-b83c-df94d9ea5ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943605203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3943605203
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.762288469
Short name T93
Test name
Test status
Simulation time 73963483 ps
CPU time 1.06 seconds
Started Aug 03 04:31:42 PM PDT 24
Finished Aug 03 04:31:43 PM PDT 24
Peak memory 204404 kb
Host smart-882d7d36-915f-4392-87f8-0fef82b30627
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762288469 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.762288469
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.895701933
Short name T68
Test name
Test status
Simulation time 190208431 ps
CPU time 0.79 seconds
Started Aug 03 04:31:41 PM PDT 24
Finished Aug 03 04:31:42 PM PDT 24
Peak memory 204252 kb
Host smart-7132879a-b25f-46af-ae47-4727e851ae0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895701933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.895701933
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2566318331
Short name T138
Test name
Test status
Simulation time 20308354 ps
CPU time 0.64 seconds
Started Aug 03 04:31:38 PM PDT 24
Finished Aug 03 04:31:39 PM PDT 24
Peak memory 204228 kb
Host smart-aaa3af65-9db6-4240-80cd-b385e1f79828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566318331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2566318331
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.8120256
Short name T49
Test name
Test status
Simulation time 41148898 ps
CPU time 0.93 seconds
Started Aug 03 04:31:38 PM PDT 24
Finished Aug 03 04:31:39 PM PDT 24
Peak memory 204412 kb
Host smart-1cee274e-0323-4375-ba1a-caec8ec96a6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8120256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_outs
tanding.8120256
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3819343291
Short name T131
Test name
Test status
Simulation time 27376474 ps
CPU time 1.43 seconds
Started Aug 03 04:31:40 PM PDT 24
Finished Aug 03 04:31:42 PM PDT 24
Peak memory 204512 kb
Host smart-d4873ccd-a7a6-4955-b2eb-ca9b21828610
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819343291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3819343291
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3228976662
Short name T69
Test name
Test status
Simulation time 97235138 ps
CPU time 2.09 seconds
Started Aug 03 04:31:43 PM PDT 24
Finished Aug 03 04:31:45 PM PDT 24
Peak memory 204376 kb
Host smart-bfe9c0ad-bcd3-4f17-83d5-74c2f3be1e56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228976662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3228976662
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3263826487
Short name T27
Test name
Test status
Simulation time 40370068 ps
CPU time 1.71 seconds
Started Aug 03 04:31:19 PM PDT 24
Finished Aug 03 04:31:21 PM PDT 24
Peak memory 204376 kb
Host smart-e559ae88-eefe-42af-8de4-b4740944eecf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263826487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3263826487
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2335819631
Short name T136
Test name
Test status
Simulation time 743120081 ps
CPU time 2.95 seconds
Started Aug 03 04:31:19 PM PDT 24
Finished Aug 03 04:31:22 PM PDT 24
Peak memory 204396 kb
Host smart-67e7c39f-8012-4d01-84e4-b99953405d65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335819631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2335819631
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.854298946
Short name T117
Test name
Test status
Simulation time 37235509 ps
CPU time 0.89 seconds
Started Aug 03 04:31:20 PM PDT 24
Finished Aug 03 04:31:21 PM PDT 24
Peak memory 204360 kb
Host smart-c4b9509c-a121-4189-858f-3d0ec5a968a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854298946 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.854298946
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2720569015
Short name T30
Test name
Test status
Simulation time 38484723 ps
CPU time 0.72 seconds
Started Aug 03 04:31:22 PM PDT 24
Finished Aug 03 04:31:23 PM PDT 24
Peak memory 204268 kb
Host smart-c8354dd3-6073-446a-bd89-ad9a55e3209f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720569015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2720569015
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3340311997
Short name T126
Test name
Test status
Simulation time 98136933 ps
CPU time 0.66 seconds
Started Aug 03 04:31:14 PM PDT 24
Finished Aug 03 04:31:15 PM PDT 24
Peak memory 204168 kb
Host smart-972cb5ea-d621-458c-be1c-9ab16f6cf3b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340311997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3340311997
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2007757023
Short name T147
Test name
Test status
Simulation time 823711034 ps
CPU time 1.08 seconds
Started Aug 03 04:31:20 PM PDT 24
Finished Aug 03 04:31:21 PM PDT 24
Peak memory 204456 kb
Host smart-c93946da-3a9b-41a8-bb90-9bdc9d18fee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007757023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2007757023
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2167614172
Short name T98
Test name
Test status
Simulation time 538348363 ps
CPU time 2.88 seconds
Started Aug 03 04:31:14 PM PDT 24
Finished Aug 03 04:31:17 PM PDT 24
Peak memory 204412 kb
Host smart-aea2e183-7352-48c9-9819-57752ffda41b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167614172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2167614172
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.463284432
Short name T65
Test name
Test status
Simulation time 83060627 ps
CPU time 1.51 seconds
Started Aug 03 04:31:17 PM PDT 24
Finished Aug 03 04:31:19 PM PDT 24
Peak memory 204448 kb
Host smart-bbf5af11-7f25-4212-b29e-481dd03b8c51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463284432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.463284432
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3346860670
Short name T156
Test name
Test status
Simulation time 15902156 ps
CPU time 0.66 seconds
Started Aug 03 04:31:39 PM PDT 24
Finished Aug 03 04:31:40 PM PDT 24
Peak memory 204176 kb
Host smart-aea2e8c7-5932-4c69-af81-dce099287122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346860670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3346860670
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2832291255
Short name T74
Test name
Test status
Simulation time 18059809 ps
CPU time 0.71 seconds
Started Aug 03 04:31:39 PM PDT 24
Finished Aug 03 04:31:40 PM PDT 24
Peak memory 204156 kb
Host smart-b66d5a29-c01d-4031-a27c-76e15aa62587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832291255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2832291255
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1152310737
Short name T96
Test name
Test status
Simulation time 19733898 ps
CPU time 0.71 seconds
Started Aug 03 04:31:53 PM PDT 24
Finished Aug 03 04:31:53 PM PDT 24
Peak memory 204228 kb
Host smart-2769c5f7-9899-4e15-9f79-f7ed51ab0532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152310737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1152310737
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.1717748308
Short name T104
Test name
Test status
Simulation time 75822358 ps
CPU time 0.68 seconds
Started Aug 03 04:31:48 PM PDT 24
Finished Aug 03 04:31:49 PM PDT 24
Peak memory 204188 kb
Host smart-9c4276c3-b672-45b7-ab83-01832b7f147d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717748308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1717748308
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.2034177927
Short name T102
Test name
Test status
Simulation time 17450645 ps
CPU time 0.68 seconds
Started Aug 03 04:31:50 PM PDT 24
Finished Aug 03 04:31:51 PM PDT 24
Peak memory 204196 kb
Host smart-1992caf4-ee7d-45cf-b1b0-ced3613ff319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034177927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.2034177927
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1770236275
Short name T121
Test name
Test status
Simulation time 60780809 ps
CPU time 0.74 seconds
Started Aug 03 04:31:48 PM PDT 24
Finished Aug 03 04:31:49 PM PDT 24
Peak memory 204240 kb
Host smart-f26ccc4f-db01-46fa-8600-17374247c369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770236275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1770236275
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.1143682404
Short name T160
Test name
Test status
Simulation time 86228243 ps
CPU time 0.69 seconds
Started Aug 03 04:31:47 PM PDT 24
Finished Aug 03 04:31:48 PM PDT 24
Peak memory 204544 kb
Host smart-bae8d3a0-e649-4e8a-b1ed-efd100a602f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143682404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1143682404
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2764794151
Short name T73
Test name
Test status
Simulation time 35662201 ps
CPU time 0.65 seconds
Started Aug 03 04:31:46 PM PDT 24
Finished Aug 03 04:31:47 PM PDT 24
Peak memory 204140 kb
Host smart-a3565c28-e63a-4e4f-b528-553c333e7788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764794151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2764794151
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.525601734
Short name T72
Test name
Test status
Simulation time 14428765 ps
CPU time 0.67 seconds
Started Aug 03 04:31:48 PM PDT 24
Finished Aug 03 04:31:49 PM PDT 24
Peak memory 204192 kb
Host smart-730aabcd-e15f-4bb4-ba74-7654240763ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525601734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.525601734
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3745021410
Short name T38
Test name
Test status
Simulation time 1033290152 ps
CPU time 1.89 seconds
Started Aug 03 04:31:21 PM PDT 24
Finished Aug 03 04:31:23 PM PDT 24
Peak memory 204440 kb
Host smart-b783296d-c5a8-479d-ae74-bc3475326a8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745021410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3745021410
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1040235667
Short name T37
Test name
Test status
Simulation time 117915187 ps
CPU time 4.67 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:23 PM PDT 24
Peak memory 204420 kb
Host smart-6463169e-a29c-46df-8924-351089289a07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040235667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1040235667
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.4161980252
Short name T109
Test name
Test status
Simulation time 16774728 ps
CPU time 0.71 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:19 PM PDT 24
Peak memory 204284 kb
Host smart-e5de780f-565e-462b-a26d-bfabbbc8a001
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161980252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.4161980252
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.159575580
Short name T52
Test name
Test status
Simulation time 24953930 ps
CPU time 1.09 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204496 kb
Host smart-2c0bbeac-c0bc-4df7-b243-35293168d2f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159575580 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.159575580
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.235937809
Short name T31
Test name
Test status
Simulation time 55965960 ps
CPU time 0.75 seconds
Started Aug 03 04:31:19 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204300 kb
Host smart-e5b98450-be63-4b88-a595-d38f193c9e87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235937809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.235937809
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3377028456
Short name T22
Test name
Test status
Simulation time 23901077 ps
CPU time 0.98 seconds
Started Aug 03 04:31:19 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204352 kb
Host smart-4ce0c29c-d4fc-469c-909c-f3ef4fff58a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377028456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3377028456
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3031599479
Short name T97
Test name
Test status
Simulation time 98192412 ps
CPU time 2.1 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204484 kb
Host smart-0b81df5b-d75f-441f-b60d-9a36f4514259
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031599479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3031599479
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2700317683
Short name T56
Test name
Test status
Simulation time 274091701 ps
CPU time 1.39 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204412 kb
Host smart-a84bd613-700b-4bf1-b722-caa6c74cd034
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700317683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2700317683
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.794056292
Short name T152
Test name
Test status
Simulation time 16857583 ps
CPU time 0.69 seconds
Started Aug 03 04:31:52 PM PDT 24
Finished Aug 03 04:31:52 PM PDT 24
Peak memory 204196 kb
Host smart-8f7a9736-6012-4c70-b53a-8ab5082f4f39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794056292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.794056292
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3896500944
Short name T83
Test name
Test status
Simulation time 17156250 ps
CPU time 0.69 seconds
Started Aug 03 04:31:47 PM PDT 24
Finished Aug 03 04:31:48 PM PDT 24
Peak memory 204324 kb
Host smart-81f78ec0-0aff-4060-bde2-2cd48c38fd64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896500944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3896500944
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3690875194
Short name T76
Test name
Test status
Simulation time 30834466 ps
CPU time 0.69 seconds
Started Aug 03 04:31:48 PM PDT 24
Finished Aug 03 04:31:49 PM PDT 24
Peak memory 204140 kb
Host smart-f80ccb80-6052-4736-b453-f9d9e34a5f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690875194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3690875194
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1299436852
Short name T148
Test name
Test status
Simulation time 26319240 ps
CPU time 0.7 seconds
Started Aug 03 04:31:48 PM PDT 24
Finished Aug 03 04:31:49 PM PDT 24
Peak memory 204244 kb
Host smart-d0349efa-39b8-4be4-9534-9f86f64d33b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299436852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1299436852
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.303450550
Short name T154
Test name
Test status
Simulation time 22433228 ps
CPU time 0.7 seconds
Started Aug 03 04:31:52 PM PDT 24
Finished Aug 03 04:31:53 PM PDT 24
Peak memory 204188 kb
Host smart-296b740c-11b2-4a8d-b0e2-eb2382609ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303450550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.303450550
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.2495566845
Short name T81
Test name
Test status
Simulation time 57390618 ps
CPU time 0.73 seconds
Started Aug 03 04:31:50 PM PDT 24
Finished Aug 03 04:31:51 PM PDT 24
Peak memory 204236 kb
Host smart-20007a89-b60a-4293-bdfe-1c1b10c7cbc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495566845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2495566845
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.2455857999
Short name T85
Test name
Test status
Simulation time 31010229 ps
CPU time 0.68 seconds
Started Aug 03 04:31:47 PM PDT 24
Finished Aug 03 04:31:48 PM PDT 24
Peak memory 204224 kb
Host smart-f0679f65-e72b-43da-8d33-8cd5e5731fae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455857999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2455857999
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.638310959
Short name T78
Test name
Test status
Simulation time 20359737 ps
CPU time 0.69 seconds
Started Aug 03 04:31:46 PM PDT 24
Finished Aug 03 04:31:47 PM PDT 24
Peak memory 204232 kb
Host smart-432ad0a4-7ec1-4225-ae70-35988012d225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638310959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.638310959
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3608282033
Short name T82
Test name
Test status
Simulation time 47612561 ps
CPU time 0.69 seconds
Started Aug 03 04:31:52 PM PDT 24
Finished Aug 03 04:31:53 PM PDT 24
Peak memory 204188 kb
Host smart-55da2da5-b2a0-459c-b627-4d68fc2102c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608282033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3608282033
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3647987091
Short name T8
Test name
Test status
Simulation time 55906011 ps
CPU time 1.28 seconds
Started Aug 03 04:31:21 PM PDT 24
Finished Aug 03 04:31:22 PM PDT 24
Peak memory 204448 kb
Host smart-6d5c108c-8487-4e3f-bb22-fe7b697fa1b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647987091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3647987091
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3374426575
Short name T164
Test name
Test status
Simulation time 2139289266 ps
CPU time 5.16 seconds
Started Aug 03 04:31:17 PM PDT 24
Finished Aug 03 04:31:23 PM PDT 24
Peak memory 204432 kb
Host smart-a8e97c36-c3ed-4c1d-8ea6-7de3db15efb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374426575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.3374426575
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2666769686
Short name T155
Test name
Test status
Simulation time 19687867 ps
CPU time 0.73 seconds
Started Aug 03 04:31:19 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204312 kb
Host smart-f49282eb-9a5f-461d-9d4c-82b8f7707efc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666769686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2666769686
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1083197477
Short name T2
Test name
Test status
Simulation time 388207913 ps
CPU time 1.14 seconds
Started Aug 03 04:31:19 PM PDT 24
Finished Aug 03 04:31:21 PM PDT 24
Peak memory 204512 kb
Host smart-4afb0b3f-35cb-4172-8aa1-a4e55ef42c8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083197477 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1083197477
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1630858648
Short name T163
Test name
Test status
Simulation time 20784069 ps
CPU time 0.68 seconds
Started Aug 03 04:31:20 PM PDT 24
Finished Aug 03 04:31:21 PM PDT 24
Peak memory 204380 kb
Host smart-624a0fb9-19b4-41b6-bf7e-af7fc7f968d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630858648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1630858648
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.70835033
Short name T133
Test name
Test status
Simulation time 17137578 ps
CPU time 0.69 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:19 PM PDT 24
Peak memory 204184 kb
Host smart-7340fc04-5c98-4a52-88a1-903ec52edd89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70835033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.70835033
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1004060920
Short name T132
Test name
Test status
Simulation time 72601396 ps
CPU time 1.07 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:19 PM PDT 24
Peak memory 204392 kb
Host smart-00706da0-e22f-44d1-869a-0b53916ebaad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004060920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1004060920
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.826184366
Short name T14
Test name
Test status
Simulation time 165610768 ps
CPU time 1.22 seconds
Started Aug 03 04:31:19 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204604 kb
Host smart-d623fee8-3f22-47c5-ac61-88a284635858
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826184366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.826184366
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1878979820
Short name T63
Test name
Test status
Simulation time 94693865 ps
CPU time 1.49 seconds
Started Aug 03 04:31:20 PM PDT 24
Finished Aug 03 04:31:22 PM PDT 24
Peak memory 204392 kb
Host smart-5f600169-4856-4b68-8467-5c7254d7272e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878979820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1878979820
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.4199101114
Short name T50
Test name
Test status
Simulation time 21516633 ps
CPU time 0.71 seconds
Started Aug 03 04:31:51 PM PDT 24
Finished Aug 03 04:31:51 PM PDT 24
Peak memory 204168 kb
Host smart-b2328b25-2532-43ba-ac74-968432c45f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199101114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4199101114
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2080668581
Short name T105
Test name
Test status
Simulation time 110060963 ps
CPU time 0.67 seconds
Started Aug 03 04:31:49 PM PDT 24
Finished Aug 03 04:31:49 PM PDT 24
Peak memory 204236 kb
Host smart-2b45d3c0-fafe-40fd-8b1c-7355a40c0dca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080668581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2080668581
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.870207467
Short name T7
Test name
Test status
Simulation time 28439004 ps
CPU time 0.67 seconds
Started Aug 03 04:31:48 PM PDT 24
Finished Aug 03 04:31:49 PM PDT 24
Peak memory 204132 kb
Host smart-81018840-4ec4-4d0b-a786-afef61d3db22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870207467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.870207467
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.3957199592
Short name T120
Test name
Test status
Simulation time 16079650 ps
CPU time 0.64 seconds
Started Aug 03 04:31:48 PM PDT 24
Finished Aug 03 04:31:49 PM PDT 24
Peak memory 204208 kb
Host smart-24237c67-9f5d-466d-8182-c75d68d2e3e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957199592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3957199592
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1437367166
Short name T139
Test name
Test status
Simulation time 17373088 ps
CPU time 0.7 seconds
Started Aug 03 04:31:51 PM PDT 24
Finished Aug 03 04:31:51 PM PDT 24
Peak memory 204232 kb
Host smart-cc374e31-1385-48f4-be7b-96b4b9a98023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437367166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1437367166
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.719181424
Short name T11
Test name
Test status
Simulation time 84766063 ps
CPU time 0.7 seconds
Started Aug 03 04:31:47 PM PDT 24
Finished Aug 03 04:31:48 PM PDT 24
Peak memory 204324 kb
Host smart-7411179c-eb8f-47ac-918d-9bbad9aaf93f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719181424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.719181424
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.3203218786
Short name T77
Test name
Test status
Simulation time 34831796 ps
CPU time 0.66 seconds
Started Aug 03 04:31:49 PM PDT 24
Finished Aug 03 04:31:50 PM PDT 24
Peak memory 204212 kb
Host smart-fda43766-807e-487b-a947-603152d45766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203218786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3203218786
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3664744296
Short name T127
Test name
Test status
Simulation time 18616523 ps
CPU time 0.75 seconds
Started Aug 03 04:31:49 PM PDT 24
Finished Aug 03 04:31:50 PM PDT 24
Peak memory 204196 kb
Host smart-aaa91492-e6c3-4cb6-b875-c95900c812b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664744296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3664744296
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.141052986
Short name T103
Test name
Test status
Simulation time 18153209 ps
CPU time 0.68 seconds
Started Aug 03 04:31:49 PM PDT 24
Finished Aug 03 04:31:50 PM PDT 24
Peak memory 204160 kb
Host smart-7f8cb4a4-506d-454f-bc69-af4d11e9b636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141052986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.141052986
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2468457398
Short name T75
Test name
Test status
Simulation time 49931474 ps
CPU time 0.64 seconds
Started Aug 03 04:31:48 PM PDT 24
Finished Aug 03 04:31:49 PM PDT 24
Peak memory 204236 kb
Host smart-ad7a4955-fea4-480b-a7ea-0ea20dbcaa45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468457398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2468457398
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3283449020
Short name T19
Test name
Test status
Simulation time 27584330 ps
CPU time 1.26 seconds
Started Aug 03 04:31:20 PM PDT 24
Finished Aug 03 04:31:22 PM PDT 24
Peak memory 212656 kb
Host smart-5eaf46d5-54ee-44ab-87b3-db468eb08ff9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283449020 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3283449020
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3822192490
Short name T40
Test name
Test status
Simulation time 26530376 ps
CPU time 0.72 seconds
Started Aug 03 04:31:19 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204280 kb
Host smart-079f8e37-b2ab-494e-ab71-e3436f2724c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822192490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3822192490
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.1397369881
Short name T143
Test name
Test status
Simulation time 16411234 ps
CPU time 0.65 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:19 PM PDT 24
Peak memory 204180 kb
Host smart-59682095-7a11-413e-830b-62513e1da5ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397369881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1397369881
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.722982400
Short name T86
Test name
Test status
Simulation time 136711864 ps
CPU time 0.89 seconds
Started Aug 03 04:31:22 PM PDT 24
Finished Aug 03 04:31:23 PM PDT 24
Peak memory 204272 kb
Host smart-7ffb4e55-8b7e-44f9-ba7f-ceb55cd0dc20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722982400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_out
standing.722982400
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2717714388
Short name T144
Test name
Test status
Simulation time 45076788 ps
CPU time 2.15 seconds
Started Aug 03 04:31:23 PM PDT 24
Finished Aug 03 04:31:25 PM PDT 24
Peak memory 204468 kb
Host smart-6aa399fa-edbb-4a46-a71b-45ea9e6054fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717714388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2717714388
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1998716196
Short name T145
Test name
Test status
Simulation time 82236063 ps
CPU time 2.07 seconds
Started Aug 03 04:31:18 PM PDT 24
Finished Aug 03 04:31:21 PM PDT 24
Peak memory 204328 kb
Host smart-316097d0-afd4-4b1a-b999-6ef2daba289b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998716196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1998716196
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.880347994
Short name T157
Test name
Test status
Simulation time 212176579 ps
CPU time 0.96 seconds
Started Aug 03 04:31:33 PM PDT 24
Finished Aug 03 04:31:34 PM PDT 24
Peak memory 204092 kb
Host smart-3ea8b053-a649-42f9-bf00-ab8c23873cb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880347994 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.880347994
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2549296186
Short name T112
Test name
Test status
Simulation time 17288301 ps
CPU time 0.78 seconds
Started Aug 03 04:31:20 PM PDT 24
Finished Aug 03 04:31:21 PM PDT 24
Peak memory 204280 kb
Host smart-af2f2fca-8a97-4333-b023-14ff7025d650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549296186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2549296186
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.636635441
Short name T84
Test name
Test status
Simulation time 93370977 ps
CPU time 0.64 seconds
Started Aug 03 04:31:21 PM PDT 24
Finished Aug 03 04:31:22 PM PDT 24
Peak memory 204320 kb
Host smart-8b9bbf6c-29f1-4fbe-98b8-1b6cb74abced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636635441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.636635441
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.4010562164
Short name T15
Test name
Test status
Simulation time 159295658 ps
CPU time 1.22 seconds
Started Aug 03 04:31:19 PM PDT 24
Finished Aug 03 04:31:20 PM PDT 24
Peak memory 204436 kb
Host smart-bc9167df-a905-4b4f-a401-716dac0148e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010562164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.4010562164
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1803082861
Short name T61
Test name
Test status
Simulation time 50841035 ps
CPU time 1.25 seconds
Started Aug 03 04:31:20 PM PDT 24
Finished Aug 03 04:31:22 PM PDT 24
Peak memory 204440 kb
Host smart-da39489b-cf44-4b8e-b48e-07a1c6bc052e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803082861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1803082861
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3834646851
Short name T142
Test name
Test status
Simulation time 70592491 ps
CPU time 1.16 seconds
Started Aug 03 04:31:27 PM PDT 24
Finished Aug 03 04:31:28 PM PDT 24
Peak memory 204452 kb
Host smart-24fbe6ab-cdaf-4d45-81f8-f7fcaa19fa10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834646851 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3834646851
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3672983784
Short name T32
Test name
Test status
Simulation time 80955704 ps
CPU time 0.74 seconds
Started Aug 03 04:31:24 PM PDT 24
Finished Aug 03 04:31:25 PM PDT 24
Peak memory 204304 kb
Host smart-76a5fb10-a260-47e9-a16d-fefe5a21af89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672983784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3672983784
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.524518377
Short name T124
Test name
Test status
Simulation time 25433765 ps
CPU time 0.68 seconds
Started Aug 03 04:31:30 PM PDT 24
Finished Aug 03 04:31:31 PM PDT 24
Peak memory 204140 kb
Host smart-b712eb24-0fbf-4e96-a15a-65f92c16a42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524518377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.524518377
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.280207748
Short name T41
Test name
Test status
Simulation time 57742459 ps
CPU time 0.83 seconds
Started Aug 03 04:31:26 PM PDT 24
Finished Aug 03 04:31:27 PM PDT 24
Peak memory 203788 kb
Host smart-4e148196-d42f-48d0-8b6b-271bb8b3190e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280207748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.280207748
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.360983717
Short name T153
Test name
Test status
Simulation time 110865301 ps
CPU time 2.02 seconds
Started Aug 03 04:31:27 PM PDT 24
Finished Aug 03 04:31:29 PM PDT 24
Peak memory 204448 kb
Host smart-d7d49bab-3661-4992-b48a-9faff9a46488
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360983717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.360983717
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2446266679
Short name T107
Test name
Test status
Simulation time 154867216 ps
CPU time 1.28 seconds
Started Aug 03 04:31:25 PM PDT 24
Finished Aug 03 04:31:26 PM PDT 24
Peak memory 204548 kb
Host smart-9c24ed91-f2d8-4ba1-bbb7-57b49e1f3a92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446266679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2446266679
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.291010683
Short name T125
Test name
Test status
Simulation time 43324267 ps
CPU time 0.83 seconds
Started Aug 03 04:31:26 PM PDT 24
Finished Aug 03 04:31:27 PM PDT 24
Peak memory 204504 kb
Host smart-8fc817a1-6d35-4e7b-9176-8a9348c3dd36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291010683 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.291010683
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.752829179
Short name T165
Test name
Test status
Simulation time 81376303 ps
CPU time 0.73 seconds
Started Aug 03 04:31:25 PM PDT 24
Finished Aug 03 04:31:26 PM PDT 24
Peak memory 204404 kb
Host smart-8d207a0e-7c36-4bc4-9360-57ec4cd929ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752829179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.752829179
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.323924484
Short name T79
Test name
Test status
Simulation time 86321416 ps
CPU time 0.68 seconds
Started Aug 03 04:31:25 PM PDT 24
Finished Aug 03 04:31:26 PM PDT 24
Peak memory 204148 kb
Host smart-e3719652-6ffc-49f3-b92b-d1ff9e33e59c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323924484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.323924484
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3952037344
Short name T99
Test name
Test status
Simulation time 37330484 ps
CPU time 0.88 seconds
Started Aug 03 04:31:23 PM PDT 24
Finished Aug 03 04:31:24 PM PDT 24
Peak memory 204460 kb
Host smart-bc31a431-018f-4000-bd22-d34f3806cf36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952037344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3952037344
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.71076784
Short name T95
Test name
Test status
Simulation time 45904089 ps
CPU time 2.39 seconds
Started Aug 03 04:31:24 PM PDT 24
Finished Aug 03 04:31:27 PM PDT 24
Peak memory 212684 kb
Host smart-37437eb6-e6c5-42cc-a31a-a21bfdb9f289
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71076784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.71076784
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.898645466
Short name T161
Test name
Test status
Simulation time 524701513 ps
CPU time 2.06 seconds
Started Aug 03 04:31:25 PM PDT 24
Finished Aug 03 04:31:27 PM PDT 24
Peak memory 204388 kb
Host smart-aea303ef-a939-4a5b-8a45-b45d124ff685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898645466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.898645466
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3073511393
Short name T20
Test name
Test status
Simulation time 61373432 ps
CPU time 0.99 seconds
Started Aug 03 04:32:04 PM PDT 24
Finished Aug 03 04:32:05 PM PDT 24
Peak memory 204300 kb
Host smart-e2787ebf-8ef6-493f-b127-712bbb970f03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073511393 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3073511393
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.386957585
Short name T44
Test name
Test status
Simulation time 20728491 ps
CPU time 0.71 seconds
Started Aug 03 04:31:33 PM PDT 24
Finished Aug 03 04:31:34 PM PDT 24
Peak memory 204312 kb
Host smart-1ff739d3-dbd3-4265-9ef2-ee70f8ff1bbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386957585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.386957585
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.4151677316
Short name T80
Test name
Test status
Simulation time 19416527 ps
CPU time 0.69 seconds
Started Aug 03 04:32:01 PM PDT 24
Finished Aug 03 04:32:02 PM PDT 24
Peak memory 204160 kb
Host smart-53a71ab2-9960-4484-b344-ffdfe7f8f5dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151677316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.4151677316
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1962986747
Short name T23
Test name
Test status
Simulation time 47715215 ps
CPU time 1.17 seconds
Started Aug 03 04:31:28 PM PDT 24
Finished Aug 03 04:31:30 PM PDT 24
Peak memory 204340 kb
Host smart-da2ba8e9-be60-4f59-9c19-56e17a6f1a2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962986747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.1962986747
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2839529427
Short name T130
Test name
Test status
Simulation time 185445601 ps
CPU time 2.62 seconds
Started Aug 03 04:31:27 PM PDT 24
Finished Aug 03 04:31:30 PM PDT 24
Peak memory 204524 kb
Host smart-94e36905-b304-4fad-836f-8fcc92937dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839529427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2839529427
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2279502825
Short name T62
Test name
Test status
Simulation time 174580950 ps
CPU time 2.07 seconds
Started Aug 03 04:31:28 PM PDT 24
Finished Aug 03 04:31:30 PM PDT 24
Peak memory 204440 kb
Host smart-27c77f9a-98a3-468f-8f5a-3dbcdfefe2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279502825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2279502825
Directory /workspace/9.i2c_tl_intg_err/latest
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