Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.01	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	15	45	75.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	15	45	75.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	336	1			T3	1		T6	1		T12	5
all_values[1]	336	1			T3	1		T6	1		T12	5
all_values[2]	336	1			T3	1		T6	1		T12	5
all_values[3]	336	1			T3	1		T6	1		T12	5
all_values[4]	336	1			T3	1		T6	1		T12	5
all_values[5]	336	1			T3	1		T6	1		T12	5
all_values[6]	336	1			T3	1		T6	1		T12	5
all_values[7]	336	1			T3	1		T6	1		T12	5
all_values[8]	336	1			T3	1		T6	1		T12	5
all_values[9]	336	1			T3	1		T6	1		T12	5
all_values[10]	336	1			T3	1		T6	1		T12	5
all_values[11]	336	1			T3	1		T6	1		T12	5
all_values[12]	336	1			T3	1		T6	1		T12	5
all_values[13]	336	1			T3	1		T6	1		T12	5
all_values[14]	336	1			T3	1		T6	1		T12	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3314

1

T3

15

T6

15

T12

50

auto[1]

1726

1

T12

25

T10

29

T11

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T3

15

T6

15

T12

9

auto[1]

3961

1

T12

66

T10

62

T11

108

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	[auto[0]]	--	--	15

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85	1			T3	1		T6	1		T12	5
all_values[0]	auto[0]	auto[1]	148	1			T10	2		T11	2		T13	3
all_values[0]	auto[1]	auto[1]	103	1			T10	3		T11	3		T13	5
all_values[1]	auto[0]	auto[0]	57	1			T3	1		T6	1		T14	1
all_values[1]	auto[0]	auto[1]	164	1			T12	4		T10	2		T11	5
all_values[1]	auto[1]	auto[1]	115	1			T12	1		T10	3		T11	3
all_values[2]	auto[0]	auto[0]	87	1			T3	1		T6	1		T12	1
all_values[2]	auto[0]	auto[1]	144	1			T12	2		T10	3		T11	2
all_values[2]	auto[1]	auto[1]	105	1			T12	2		T10	2		T11	3
all_values[3]	auto[0]	auto[0]	73	1			T3	1		T6	1		T12	1
all_values[3]	auto[0]	auto[1]	142	1			T12	3		T10	3		T11	6
all_values[3]	auto[1]	auto[1]	121	1			T12	1		T11	2		T13	5
all_values[4]	auto[0]	auto[0]	71	1			T3	1		T6	1		T14	1
all_values[4]	auto[0]	auto[1]	150	1			T12	3		T10	3		T11	4
all_values[4]	auto[1]	auto[1]	115	1			T12	2		T10	2		T11	4
all_values[5]	auto[0]	auto[0]	45	1			T3	1		T6	1		T14	1
all_values[5]	auto[0]	auto[1]	139	1			T12	1		T10	1		T11	5
all_values[5]	auto[1]	auto[1]	152	1			T12	4		T10	3		T13	6
all_values[6]	auto[0]	auto[0]	91	1			T3	1		T6	1		T14	1
all_values[6]	auto[0]	auto[1]	133	1			T12	3		T10	3		T11	7
all_values[6]	auto[1]	auto[1]	112	1			T12	2		T10	1		T13	3
all_values[7]	auto[0]	auto[0]	72	1			T3	1		T6	1		T14	1
all_values[7]	auto[0]	auto[1]	146	1			T12	3		T10	4		T11	6
all_values[7]	auto[1]	auto[1]	118	1			T12	2		T11	1		T13	4
all_values[8]	auto[0]	auto[0]	69	1			T3	1		T6	1		T12	1
all_values[8]	auto[0]	auto[1]	150	1			T12	1		T10	3		T11	7
all_values[8]	auto[1]	auto[1]	117	1			T12	3		T10	1		T11	1
all_values[9]	auto[0]	auto[0]	71	1			T3	1		T6	1		T14	1
all_values[9]	auto[0]	auto[1]	154	1			T12	4		T11	7		T13	4
all_values[9]	auto[1]	auto[1]	111	1			T12	1		T11	1		T13	3
all_values[10]	auto[0]	auto[0]	70	1			T3	1		T6	1		T14	1
all_values[10]	auto[0]	auto[1]	161	1			T12	4		T10	3		T11	4
all_values[10]	auto[1]	auto[1]	105	1			T12	1		T10	2		T11	4
all_values[11]	auto[0]	auto[0]	54	1			T3	1		T6	1		T14	1
all_values[11]	auto[0]	auto[1]	169	1			T12	3		T10	2		T11	3
all_values[11]	auto[1]	auto[1]	113	1			T12	2		T10	3		T11	5
all_values[12]	auto[0]	auto[0]	64	1			T3	1		T6	1		T14	1
all_values[12]	auto[0]	auto[1]	166	1			T12	4		T10	2		T11	5
all_values[12]	auto[1]	auto[1]	106	1			T12	1		T10	1		T11	2
all_values[13]	auto[0]	auto[0]	88	1			T3	1		T6	1		T12	1
all_values[13]	auto[0]	auto[1]	129	1			T12	3		T10	1		T11	6
all_values[13]	auto[1]	auto[1]	119	1			T12	1		T10	4		T11	2
all_values[14]	auto[0]	auto[0]	82	1			T3	1		T6	1		T14	1
all_values[14]	auto[0]	auto[1]	140	1			T12	3		T10	1		T11	4
all_values[14]	auto[1]	auto[1]	114	1			T12	2		T10	4		T11	4