Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
52.69	40.66	40.76	90.72	0.00	42.98	99.68	54.00

Total tests in report: 164

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
45.09	45.09	39.00	39.00	36.13	36.13	89.08	89.08	0.00	0.00	41.77	41.77	91.08	91.08	18.53	18.53	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2620632596
50.11	5.03	40.20	1.19	38.31	2.18	92.06	2.98	0.00	0.00	42.91	1.13	91.72	0.64	45.58	27.05	/workspace/coverage/cover_reg_top/14.i2c_intr_test.3204056458
51.75	1.64	40.20	0.00	39.89	1.58	94.04	1.99	0.00	0.00	42.98	0.07	96.82	5.10	48.32	2.74	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1562224355
52.31	0.57	40.20	0.00	39.89	0.00	95.16	1.12	0.00	0.00	42.98	0.00	96.82	0.00	51.16	2.84	/workspace/coverage/cover_reg_top/2.i2c_intr_test.690803548
52.68	0.36	40.20	0.00	39.89	0.00	95.16	0.00	0.00	0.00	42.98	0.00	99.36	2.55	51.16	0.00	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2182733675
52.94	0.27	40.20	0.00	39.89	0.00	97.02	1.86	0.00	0.00	42.98	0.00	99.36	0.00	51.16	0.00	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3385344731
53.08	0.14	40.20	0.00	39.89	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.36	0.00	52.11	0.95	/workspace/coverage/cover_reg_top/4.i2c_intr_test.924274630
53.21	0.13	40.66	0.46	40.12	0.23	97.02	0.00	0.00	0.00	42.98	0.00	99.36	0.00	52.32	0.21	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4026609964
53.29	0.08	40.66	0.00	40.27	0.15	97.02	0.00	0.00	0.00	42.98	0.00	99.36	0.00	52.74	0.42	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2613101503
53.35	0.06	40.66	0.00	40.27	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.32	52.84	0.11	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.3845470423
53.41	0.06	40.66	0.00	40.27	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.26	0.42	/workspace/coverage/cover_reg_top/23.i2c_intr_test.2827289192
53.46	0.05	40.66	0.00	40.27	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.58	0.32	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2936314288
53.50	0.04	40.66	0.00	40.46	0.19	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.68	0.11	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2451953707
53.53	0.03	40.66	0.00	40.57	0.11	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.79	0.11	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.896909180
53.55	0.02	40.66	0.00	40.72	0.15	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.79	0.00	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.1010924461
53.57	0.02	40.66	0.00	40.72	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.89	0.11	/workspace/coverage/cover_reg_top/0.i2c_intr_test.3477645780
53.58	0.02	40.66	0.00	40.72	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	54.00	0.11	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3893931634
53.59	0.01	40.66	0.00	40.76	0.04	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	54.00	0.00	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2987098778

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.174597450
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1127688000
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2417543863
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1413528792
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2550590683
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.432941846
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4087142405
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1526038738
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2277876102
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1250480857
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.701494110
/workspace/coverage/cover_reg_top/1.i2c_intr_test.1044172116
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1549662876
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.4059409747
/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3345421851
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.451389127
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1491673533
/workspace/coverage/cover_reg_top/10.i2c_intr_test.1082764828
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.438446164
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.880805592
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2129539766
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2706524590
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.4230965968
/workspace/coverage/cover_reg_top/11.i2c_intr_test.3575141562
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3091813117
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.158162666
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1801995551
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.943473269
/workspace/coverage/cover_reg_top/12.i2c_intr_test.3391067579
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2341109739
/workspace/coverage/cover_reg_top/13.i2c_intr_test.2253482226
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3721638482
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2550367068
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.696963615
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.92115379
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.1329043425
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2811424559
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.638534806
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2005907769
/workspace/coverage/cover_reg_top/15.i2c_intr_test.852134099
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2808330150
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.3076131591
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2497869229
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1714995690
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2308153386
/workspace/coverage/cover_reg_top/16.i2c_intr_test.4233773874
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.839567968
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.1929328344
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1347601260
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1024010131
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2173516341
/workspace/coverage/cover_reg_top/17.i2c_intr_test.1425742100
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.173587787
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2813458080
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.687080134
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2036298134
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.2267064166
/workspace/coverage/cover_reg_top/18.i2c_intr_test.292622117
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2779692009
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2926450913
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2976355494
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2967104853
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.845479792
/workspace/coverage/cover_reg_top/19.i2c_intr_test.2861780718
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3783688772
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.2353345769
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.371591993
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1789678250
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.517702863
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2535520794
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.227877491
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2726920378
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2782839557
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.2222541407
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3583577419
/workspace/coverage/cover_reg_top/20.i2c_intr_test.1590024302
/workspace/coverage/cover_reg_top/21.i2c_intr_test.464260806
/workspace/coverage/cover_reg_top/22.i2c_intr_test.3972170429
/workspace/coverage/cover_reg_top/24.i2c_intr_test.3800834038
/workspace/coverage/cover_reg_top/25.i2c_intr_test.315971902
/workspace/coverage/cover_reg_top/26.i2c_intr_test.4060424384
/workspace/coverage/cover_reg_top/27.i2c_intr_test.1900338656
/workspace/coverage/cover_reg_top/28.i2c_intr_test.2312840976
/workspace/coverage/cover_reg_top/29.i2c_intr_test.1271711189
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4182229496
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2261979618
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3596729433
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.834092326
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.3258759043
/workspace/coverage/cover_reg_top/3.i2c_intr_test.305357407
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2647004874
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2734379902
/workspace/coverage/cover_reg_top/30.i2c_intr_test.2455667269
/workspace/coverage/cover_reg_top/31.i2c_intr_test.3613468981
/workspace/coverage/cover_reg_top/32.i2c_intr_test.286502523
/workspace/coverage/cover_reg_top/33.i2c_intr_test.3993047520
/workspace/coverage/cover_reg_top/34.i2c_intr_test.2494184588
/workspace/coverage/cover_reg_top/35.i2c_intr_test.2643924933
/workspace/coverage/cover_reg_top/36.i2c_intr_test.440741044
/workspace/coverage/cover_reg_top/37.i2c_intr_test.4021532706
/workspace/coverage/cover_reg_top/38.i2c_intr_test.446135248
/workspace/coverage/cover_reg_top/39.i2c_intr_test.1017954518
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2207339110
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3242603823
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1873152427
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1593196564
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.1014381301
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3615537065
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.277339630
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.623797482
/workspace/coverage/cover_reg_top/40.i2c_intr_test.753485792
/workspace/coverage/cover_reg_top/41.i2c_intr_test.1211022475
/workspace/coverage/cover_reg_top/42.i2c_intr_test.1998927315
/workspace/coverage/cover_reg_top/43.i2c_intr_test.3241154814
/workspace/coverage/cover_reg_top/44.i2c_intr_test.1373744924
/workspace/coverage/cover_reg_top/45.i2c_intr_test.3272337810
/workspace/coverage/cover_reg_top/46.i2c_intr_test.4180482928
/workspace/coverage/cover_reg_top/47.i2c_intr_test.3738314879
/workspace/coverage/cover_reg_top/48.i2c_intr_test.3459664428
/workspace/coverage/cover_reg_top/49.i2c_intr_test.4088738984
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.670420612
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.2176095905
/workspace/coverage/cover_reg_top/5.i2c_intr_test.2833273106
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2971886599
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.946087737
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3060656729
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.130634652
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.1182365860
/workspace/coverage/cover_reg_top/6.i2c_intr_test.2398468262
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.3976063451
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1905549799
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1428193212
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3677739463
/workspace/coverage/cover_reg_top/7.i2c_intr_test.637156408
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.4100156233
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1378722203
/workspace/coverage/cover_reg_top/8.i2c_intr_test.165548784
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2763203091
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.170028311
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4002385949
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.279777841
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.278540776
/workspace/coverage/cover_reg_top/9.i2c_intr_test.1828484607
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1114674183
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3691206177
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1613354039

Total test records in report: 164

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.2176095905	Aug 04 04:31:38 PM PDT 24	Aug 04 04:31:39 PM PDT 24	63134555 ps
T2	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.158162666	Aug 04 04:32:00 PM PDT 24	Aug 04 04:32:01 PM PDT 24	409901352 ps
T3	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.277339630	Aug 04 04:31:44 PM PDT 24	Aug 04 04:31:46 PM PDT 24	109002626 ps
T7	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.2267064166	Aug 04 04:32:09 PM PDT 24	Aug 04 04:32:09 PM PDT 24	16441088 ps
T8	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.943473269	Aug 04 04:32:12 PM PDT 24	Aug 04 04:32:13 PM PDT 24	26271623 ps
T6	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.3976063451	Aug 04 04:31:55 PM PDT 24	Aug 04 04:31:56 PM PDT 24	126734745 ps
T4	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2620632596	Aug 04 04:31:51 PM PDT 24	Aug 04 04:31:54 PM PDT 24	456445838 ps
T12	/workspace/coverage/cover_reg_top/40.i2c_intr_test.753485792	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:09 PM PDT 24	47162482 ps
T14	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.4100156233	Aug 04 04:32:12 PM PDT 24	Aug 04 04:32:13 PM PDT 24	62247359 ps
T5	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3345421851	Aug 04 04:31:51 PM PDT 24	Aug 04 04:31:53 PM PDT 24	646037430 ps
T9	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4026609964	Aug 04 04:31:46 PM PDT 24	Aug 04 04:31:47 PM PDT 24	25638024 ps
T10	/workspace/coverage/cover_reg_top/29.i2c_intr_test.1271711189	Aug 04 04:32:13 PM PDT 24	Aug 04 04:32:14 PM PDT 24	30337049 ps
T55	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3721638482	Aug 04 04:32:17 PM PDT 24	Aug 04 04:32:18 PM PDT 24	62328863 ps
T21	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.834092326	Aug 04 04:31:57 PM PDT 24	Aug 04 04:31:59 PM PDT 24	53782492 ps
T15	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.1010924461	Aug 04 04:31:58 PM PDT 24	Aug 04 04:32:01 PM PDT 24	328207092 ps
T11	/workspace/coverage/cover_reg_top/35.i2c_intr_test.2643924933	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:07 PM PDT 24	18557067 ps
T13	/workspace/coverage/cover_reg_top/14.i2c_intr_test.3204056458	Aug 04 04:32:04 PM PDT 24	Aug 04 04:32:05 PM PDT 24	21550634 ps
T56	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2550590683	Aug 04 04:32:11 PM PDT 24	Aug 04 04:32:12 PM PDT 24	192122654 ps
T16	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1562224355	Aug 04 04:32:10 PM PDT 24	Aug 04 04:32:12 PM PDT 24	113269487 ps
T17	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.670420612	Aug 04 04:32:02 PM PDT 24	Aug 04 04:32:03 PM PDT 24	29047793 ps
T18	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2497869229	Aug 04 04:32:01 PM PDT 24	Aug 04 04:32:03 PM PDT 24	83595854 ps
T19	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.687080134	Aug 04 04:32:04 PM PDT 24	Aug 04 04:32:06 PM PDT 24	97528425 ps
T59	/workspace/coverage/cover_reg_top/15.i2c_intr_test.852134099	Aug 04 04:32:02 PM PDT 24	Aug 04 04:32:02 PM PDT 24	17204496 ps
T23	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3385344731	Aug 04 04:31:32 PM PDT 24	Aug 04 04:31:34 PM PDT 24	119235996 ps
T64	/workspace/coverage/cover_reg_top/5.i2c_intr_test.2833273106	Aug 04 04:32:02 PM PDT 24	Aug 04 04:32:03 PM PDT 24	53117082 ps
T63	/workspace/coverage/cover_reg_top/39.i2c_intr_test.1017954518	Aug 04 04:32:20 PM PDT 24	Aug 04 04:32:20 PM PDT 24	17167911 ps
T20	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1801995551	Aug 04 04:31:59 PM PDT 24	Aug 04 04:32:00 PM PDT 24	71240659 ps
T65	/workspace/coverage/cover_reg_top/42.i2c_intr_test.1998927315	Aug 04 04:32:10 PM PDT 24	Aug 04 04:32:11 PM PDT 24	31078822 ps
T22	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.2353345769	Aug 04 04:32:14 PM PDT 24	Aug 04 04:32:17 PM PDT 24	669650104 ps
T83	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1714995690	Aug 04 04:32:03 PM PDT 24	Aug 04 04:32:04 PM PDT 24	25988602 ps
T79	/workspace/coverage/cover_reg_top/4.i2c_intr_test.924274630	Aug 04 04:31:54 PM PDT 24	Aug 04 04:31:55 PM PDT 24	16277611 ps
T24	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2182733675	Aug 04 04:31:53 PM PDT 24	Aug 04 04:31:54 PM PDT 24	54775818 ps
T31	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2706524590	Aug 04 04:31:57 PM PDT 24	Aug 04 04:31:58 PM PDT 24	27217483 ps
T32	/workspace/coverage/cover_reg_top/2.i2c_intr_test.690803548	Aug 04 04:31:44 PM PDT 24	Aug 04 04:31:45 PM PDT 24	51143276 ps
T33	/workspace/coverage/cover_reg_top/19.i2c_intr_test.2861780718	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:07 PM PDT 24	17248333 ps
T34	/workspace/coverage/cover_reg_top/12.i2c_intr_test.3391067579	Aug 04 04:32:13 PM PDT 24	Aug 04 04:32:13 PM PDT 24	44968662 ps
T25	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2207339110	Aug 04 04:31:50 PM PDT 24	Aug 04 04:31:51 PM PDT 24	96499502 ps
T35	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4002385949	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:09 PM PDT 24	86884836 ps
T36	/workspace/coverage/cover_reg_top/24.i2c_intr_test.3800834038	Aug 04 04:31:59 PM PDT 24	Aug 04 04:32:00 PM PDT 24	30393821 ps
T26	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2613101503	Aug 04 04:32:04 PM PDT 24	Aug 04 04:32:05 PM PDT 24	108354354 ps
T37	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.227877491	Aug 04 04:31:38 PM PDT 24	Aug 04 04:31:39 PM PDT 24	28494646 ps
T60	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3691206177	Aug 04 04:32:04 PM PDT 24	Aug 04 04:32:06 PM PDT 24	389032441 ps
T57	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3615537065	Aug 04 04:31:49 PM PDT 24	Aug 04 04:31:50 PM PDT 24	79874746 ps
T27	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1789678250	Aug 04 04:31:39 PM PDT 24	Aug 04 04:31:40 PM PDT 24	117694883 ps
T84	/workspace/coverage/cover_reg_top/26.i2c_intr_test.4060424384	Aug 04 04:32:17 PM PDT 24	Aug 04 04:32:18 PM PDT 24	43989366 ps
T61	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.946087737	Aug 04 04:31:37 PM PDT 24	Aug 04 04:31:39 PM PDT 24	551528297 ps
T58	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.92115379	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:09 PM PDT 24	100826097 ps
T62	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2308153386	Aug 04 04:32:10 PM PDT 24	Aug 04 04:32:11 PM PDT 24	46532267 ps
T80	/workspace/coverage/cover_reg_top/7.i2c_intr_test.637156408	Aug 04 04:31:46 PM PDT 24	Aug 04 04:31:46 PM PDT 24	31824554 ps
T28	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1873152427	Aug 04 04:31:59 PM PDT 24	Aug 04 04:32:00 PM PDT 24	26047273 ps
T29	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.278540776	Aug 04 04:32:00 PM PDT 24	Aug 04 04:32:01 PM PDT 24	19468057 ps
T30	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1549662876	Aug 04 04:31:46 PM PDT 24	Aug 04 04:31:47 PM PDT 24	127174105 ps
T46	/workspace/coverage/cover_reg_top/25.i2c_intr_test.315971902	Aug 04 04:32:16 PM PDT 24	Aug 04 04:32:16 PM PDT 24	70828779 ps
T47	/workspace/coverage/cover_reg_top/31.i2c_intr_test.3613468981	Aug 04 04:32:14 PM PDT 24	Aug 04 04:32:15 PM PDT 24	22523933 ps
T48	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.371591993	Aug 04 04:32:05 PM PDT 24	Aug 04 04:32:07 PM PDT 24	53591668 ps
T49	/workspace/coverage/cover_reg_top/0.i2c_intr_test.3477645780	Aug 04 04:31:28 PM PDT 24	Aug 04 04:31:28 PM PDT 24	47768251 ps
T50	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3893931634	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:08 PM PDT 24	80449139 ps
T51	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.3258759043	Aug 04 04:31:34 PM PDT 24	Aug 04 04:31:34 PM PDT 24	97678000 ps
T52	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2535520794	Aug 04 04:31:36 PM PDT 24	Aug 04 04:31:37 PM PDT 24	24956308 ps
T82	/workspace/coverage/cover_reg_top/23.i2c_intr_test.2827289192	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:07 PM PDT 24	31880331 ps
T74	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2779692009	Aug 04 04:32:11 PM PDT 24	Aug 04 04:32:12 PM PDT 24	329102049 ps
T85	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2926450913	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:10 PM PDT 24	106667570 ps
T86	/workspace/coverage/cover_reg_top/41.i2c_intr_test.1211022475	Aug 04 04:32:12 PM PDT 24	Aug 04 04:32:13 PM PDT 24	51187215 ps
T87	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.279777841	Aug 04 04:31:57 PM PDT 24	Aug 04 04:31:58 PM PDT 24	53174549 ps
T88	/workspace/coverage/cover_reg_top/3.i2c_intr_test.305357407	Aug 04 04:31:41 PM PDT 24	Aug 04 04:31:42 PM PDT 24	18623524 ps
T73	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2987098778	Aug 04 04:32:07 PM PDT 24	Aug 04 04:32:09 PM PDT 24	388449144 ps
T89	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.4059409747	Aug 04 04:31:49 PM PDT 24	Aug 04 04:31:50 PM PDT 24	25199730 ps
T90	/workspace/coverage/cover_reg_top/10.i2c_intr_test.1082764828	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:07 PM PDT 24	19748922 ps
T91	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1378722203	Aug 04 04:32:00 PM PDT 24	Aug 04 04:32:01 PM PDT 24	93116295 ps
T67	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1613354039	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:11 PM PDT 24	465536127 ps
T81	/workspace/coverage/cover_reg_top/22.i2c_intr_test.3972170429	Aug 04 04:32:13 PM PDT 24	Aug 04 04:32:13 PM PDT 24	41633312 ps
T92	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1413528792	Aug 04 04:31:35 PM PDT 24	Aug 04 04:31:36 PM PDT 24	69583101 ps
T93	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2971886599	Aug 04 04:32:18 PM PDT 24	Aug 04 04:32:19 PM PDT 24	69114008 ps
T94	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1250480857	Aug 04 04:31:54 PM PDT 24	Aug 04 04:31:55 PM PDT 24	32834686 ps
T95	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2417543863	Aug 04 04:31:35 PM PDT 24	Aug 04 04:31:47 PM PDT 24	25542241 ps
T96	/workspace/coverage/cover_reg_top/47.i2c_intr_test.3738314879	Aug 04 04:32:04 PM PDT 24	Aug 04 04:32:05 PM PDT 24	38462729 ps
T97	/workspace/coverage/cover_reg_top/37.i2c_intr_test.4021532706	Aug 04 04:31:58 PM PDT 24	Aug 04 04:31:59 PM PDT 24	16628916 ps
T98	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2967104853	Aug 04 04:32:02 PM PDT 24	Aug 04 04:32:03 PM PDT 24	121322622 ps
T38	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1526038738	Aug 04 04:31:48 PM PDT 24	Aug 04 04:31:49 PM PDT 24	89735863 ps
T99	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.1014381301	Aug 04 04:31:48 PM PDT 24	Aug 04 04:31:54 PM PDT 24	29737085 ps
T100	/workspace/coverage/cover_reg_top/44.i2c_intr_test.1373744924	Aug 04 04:31:59 PM PDT 24	Aug 04 04:32:00 PM PDT 24	16669816 ps
T101	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2734379902	Aug 04 04:31:42 PM PDT 24	Aug 04 04:31:48 PM PDT 24	81355023 ps
T102	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3091813117	Aug 04 04:31:46 PM PDT 24	Aug 04 04:31:47 PM PDT 24	88815095 ps
T39	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.3845470423	Aug 04 04:32:05 PM PDT 24	Aug 04 04:32:06 PM PDT 24	95332265 ps
T103	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2036298134	Aug 04 04:32:00 PM PDT 24	Aug 04 04:32:01 PM PDT 24	25385133 ps
T66	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.896909180	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:08 PM PDT 24	126793941 ps
T104	/workspace/coverage/cover_reg_top/8.i2c_intr_test.165548784	Aug 04 04:31:52 PM PDT 24	Aug 04 04:31:53 PM PDT 24	136423540 ps
T105	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.4230965968	Aug 04 04:32:02 PM PDT 24	Aug 04 04:32:03 PM PDT 24	24765044 ps
T106	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3060656729	Aug 04 04:31:29 PM PDT 24	Aug 04 04:31:30 PM PDT 24	272764811 ps
T40	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2173516341	Aug 04 04:32:09 PM PDT 24	Aug 04 04:32:10 PM PDT 24	250087750 ps
T69	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2811424559	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:08 PM PDT 24	228725922 ps
T107	/workspace/coverage/cover_reg_top/11.i2c_intr_test.3575141562	Aug 04 04:31:41 PM PDT 24	Aug 04 04:31:41 PM PDT 24	16401368 ps
T108	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.3076131591	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:08 PM PDT 24	297497741 ps
T109	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2813458080	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:09 PM PDT 24	74705544 ps
T110	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1024010131	Aug 04 04:32:10 PM PDT 24	Aug 04 04:32:11 PM PDT 24	26081532 ps
T111	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1114674183	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:09 PM PDT 24	54926985 ps
T112	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.432941846	Aug 04 04:31:59 PM PDT 24	Aug 04 04:32:01 PM PDT 24	1399457036 ps
T113	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2341109739	Aug 04 04:32:12 PM PDT 24	Aug 04 04:32:13 PM PDT 24	129169709 ps
T41	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4182229496	Aug 04 04:31:54 PM PDT 24	Aug 04 04:31:55 PM PDT 24	90037917 ps
T114	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.173587787	Aug 04 04:32:13 PM PDT 24	Aug 04 04:32:14 PM PDT 24	63987150 ps
T115	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1491673533	Aug 04 04:31:52 PM PDT 24	Aug 04 04:31:53 PM PDT 24	71244173 ps
T75	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2808330150	Aug 04 04:32:04 PM PDT 24	Aug 04 04:32:05 PM PDT 24	73848246 ps
T116	/workspace/coverage/cover_reg_top/49.i2c_intr_test.4088738984	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:09 PM PDT 24	15377999 ps
T117	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.451389127	Aug 04 04:31:53 PM PDT 24	Aug 04 04:31:55 PM PDT 24	43143095 ps
T118	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2976355494	Aug 04 04:32:09 PM PDT 24	Aug 04 04:32:11 PM PDT 24	158305090 ps
T119	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2782839557	Aug 04 04:32:09 PM PDT 24	Aug 04 04:32:10 PM PDT 24	69331512 ps
T120	/workspace/coverage/cover_reg_top/38.i2c_intr_test.446135248	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:09 PM PDT 24	33437505 ps
T121	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2129539766	Aug 04 04:31:56 PM PDT 24	Aug 04 04:31:57 PM PDT 24	82920014 ps
T42	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.701494110	Aug 04 04:31:45 PM PDT 24	Aug 04 04:31:46 PM PDT 24	50620158 ps
T43	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3596729433	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:09 PM PDT 24	28408359 ps
T122	/workspace/coverage/cover_reg_top/33.i2c_intr_test.3993047520	Aug 04 04:32:11 PM PDT 24	Aug 04 04:32:11 PM PDT 24	30533761 ps
T123	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.696963615	Aug 04 04:32:12 PM PDT 24	Aug 04 04:32:13 PM PDT 24	39963905 ps
T124	/workspace/coverage/cover_reg_top/30.i2c_intr_test.2455667269	Aug 04 04:32:13 PM PDT 24	Aug 04 04:32:14 PM PDT 24	25187256 ps
T125	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2550367068	Aug 04 04:32:04 PM PDT 24	Aug 04 04:32:06 PM PDT 24	63860311 ps
T126	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2726920378	Aug 04 04:31:28 PM PDT 24	Aug 04 04:31:29 PM PDT 24	27790898 ps
T127	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.880805592	Aug 04 04:32:00 PM PDT 24	Aug 04 04:32:03 PM PDT 24	98553332 ps
T72	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.623797482	Aug 04 04:31:40 PM PDT 24	Aug 04 04:31:42 PM PDT 24	127821611 ps
T128	/workspace/coverage/cover_reg_top/43.i2c_intr_test.3241154814	Aug 04 04:32:14 PM PDT 24	Aug 04 04:32:15 PM PDT 24	39397765 ps
T129	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3783688772	Aug 04 04:31:56 PM PDT 24	Aug 04 04:31:57 PM PDT 24	65454263 ps
T130	/workspace/coverage/cover_reg_top/13.i2c_intr_test.2253482226	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:07 PM PDT 24	26975943 ps
T131	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.438446164	Aug 04 04:31:52 PM PDT 24	Aug 04 04:31:53 PM PDT 24	145981764 ps
T132	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.130634652	Aug 04 04:31:49 PM PDT 24	Aug 04 04:31:50 PM PDT 24	35637769 ps
T133	/workspace/coverage/cover_reg_top/28.i2c_intr_test.2312840976	Aug 04 04:32:03 PM PDT 24	Aug 04 04:32:04 PM PDT 24	19146138 ps
T134	/workspace/coverage/cover_reg_top/32.i2c_intr_test.286502523	Aug 04 04:32:11 PM PDT 24	Aug 04 04:32:12 PM PDT 24	15793957 ps
T135	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.517702863	Aug 04 04:31:54 PM PDT 24	Aug 04 04:31:57 PM PDT 24	355453555 ps
T136	/workspace/coverage/cover_reg_top/34.i2c_intr_test.2494184588	Aug 04 04:32:14 PM PDT 24	Aug 04 04:32:15 PM PDT 24	16836753 ps
T137	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.638534806	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:10 PM PDT 24	41671153 ps
T44	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.845479792	Aug 04 04:31:55 PM PDT 24	Aug 04 04:31:56 PM PDT 24	25849702 ps
T138	/workspace/coverage/cover_reg_top/27.i2c_intr_test.1900338656	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:07 PM PDT 24	29836576 ps
T139	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.2222541407	Aug 04 04:31:59 PM PDT 24	Aug 04 04:32:01 PM PDT 24	33233811 ps
T140	/workspace/coverage/cover_reg_top/36.i2c_intr_test.440741044	Aug 04 04:32:03 PM PDT 24	Aug 04 04:32:04 PM PDT 24	35631976 ps
T141	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.170028311	Aug 04 04:31:58 PM PDT 24	Aug 04 04:32:00 PM PDT 24	59957271 ps
T142	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1593196564	Aug 04 04:32:11 PM PDT 24	Aug 04 04:32:17 PM PDT 24	39810619 ps
T68	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1905549799	Aug 04 04:32:06 PM PDT 24	Aug 04 04:32:07 PM PDT 24	458959214 ps
T143	/workspace/coverage/cover_reg_top/18.i2c_intr_test.292622117	Aug 04 04:32:01 PM PDT 24	Aug 04 04:32:02 PM PDT 24	33261333 ps
T144	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.1329043425	Aug 04 04:32:03 PM PDT 24	Aug 04 04:32:06 PM PDT 24	168371862 ps
T145	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2277876102	Aug 04 04:31:54 PM PDT 24	Aug 04 04:31:59 PM PDT 24	372718321 ps
T146	/workspace/coverage/cover_reg_top/48.i2c_intr_test.3459664428	Aug 04 04:32:10 PM PDT 24	Aug 04 04:32:11 PM PDT 24	16156464 ps
T147	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.1182365860	Aug 04 04:31:58 PM PDT 24	Aug 04 04:31:59 PM PDT 24	24158493 ps
T45	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1127688000	Aug 04 04:31:21 PM PDT 24	Aug 04 04:31:23 PM PDT 24	48980389 ps
T148	/workspace/coverage/cover_reg_top/17.i2c_intr_test.1425742100	Aug 04 04:31:53 PM PDT 24	Aug 04 04:31:54 PM PDT 24	34941919 ps
T149	/workspace/coverage/cover_reg_top/9.i2c_intr_test.1828484607	Aug 04 04:31:48 PM PDT 24	Aug 04 04:31:49 PM PDT 24	18801448 ps
T150	/workspace/coverage/cover_reg_top/46.i2c_intr_test.4180482928	Aug 04 04:32:16 PM PDT 24	Aug 04 04:32:17 PM PDT 24	21750810 ps
T70	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2451953707	Aug 04 04:31:39 PM PDT 24	Aug 04 04:31:41 PM PDT 24	124838825 ps
T53	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.174597450	Aug 04 04:32:00 PM PDT 24	Aug 04 04:32:02 PM PDT 24	116287120 ps
T71	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3583577419	Aug 04 04:32:04 PM PDT 24	Aug 04 04:32:05 PM PDT 24	141659681 ps
T151	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4087142405	Aug 04 04:31:52 PM PDT 24	Aug 04 04:31:54 PM PDT 24	124400665 ps
T152	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.1929328344	Aug 04 04:32:10 PM PDT 24	Aug 04 04:32:13 PM PDT 24	211010766 ps
T153	/workspace/coverage/cover_reg_top/20.i2c_intr_test.1590024302	Aug 04 04:32:19 PM PDT 24	Aug 04 04:32:20 PM PDT 24	18463840 ps
T154	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2005907769	Aug 04 04:32:04 PM PDT 24	Aug 04 04:32:05 PM PDT 24	31367534 ps
T155	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2261979618	Aug 04 04:31:41 PM PDT 24	Aug 04 04:31:44 PM PDT 24	121156679 ps
T156	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2763203091	Aug 04 04:32:14 PM PDT 24	Aug 04 04:32:14 PM PDT 24	40184787 ps
T157	/workspace/coverage/cover_reg_top/45.i2c_intr_test.3272337810	Aug 04 04:32:00 PM PDT 24	Aug 04 04:32:01 PM PDT 24	20228084 ps
T76	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2936314288	Aug 04 04:31:51 PM PDT 24	Aug 04 04:31:53 PM PDT 24	47884121 ps
T54	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3242603823	Aug 04 04:31:57 PM PDT 24	Aug 04 04:32:02 PM PDT 24	513695712 ps
T158	/workspace/coverage/cover_reg_top/21.i2c_intr_test.464260806	Aug 04 04:32:11 PM PDT 24	Aug 04 04:32:12 PM PDT 24	46350062 ps
T77	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2647004874	Aug 04 04:31:43 PM PDT 24	Aug 04 04:31:44 PM PDT 24	225995613 ps
T78	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.839567968	Aug 04 04:31:57 PM PDT 24	Aug 04 04:31:58 PM PDT 24	55145553 ps
T159	/workspace/coverage/cover_reg_top/16.i2c_intr_test.4233773874	Aug 04 04:32:08 PM PDT 24	Aug 04 04:32:09 PM PDT 24	18505002 ps
T160	/workspace/coverage/cover_reg_top/6.i2c_intr_test.2398468262	Aug 04 04:31:46 PM PDT 24	Aug 04 04:31:47 PM PDT 24	43078199 ps
T161	/workspace/coverage/cover_reg_top/1.i2c_intr_test.1044172116	Aug 04 04:31:46 PM PDT 24	Aug 04 04:31:47 PM PDT 24	25041802 ps
T162	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3677739463	Aug 04 04:32:04 PM PDT 24	Aug 04 04:32:05 PM PDT 24	21635183 ps
T163	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1428193212	Aug 04 04:31:42 PM PDT 24	Aug 04 04:31:43 PM PDT 24	113084268 ps
T164	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1347601260	Aug 04 04:31:55 PM PDT 24	Aug 04 04:31:56 PM PDT 24	83853118 ps

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2620632596
Short name	T4
Test name
Test status
Simulation time	456445838 ps
CPU time	2.29 seconds
Started	Aug 04 04:31:51 PM PDT 24
Finished	Aug 04 04:31:54 PM PDT 24
Peak memory	204524 kb
Host	smart-e54ea074-20c6-479b-a247-3f70bcdfa99a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620632596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2620632596
Directory	/workspace/3.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_intr_test.3204056458
Short name	T13
Test name
Test status
Simulation time	21550634 ps
CPU time	0.68 seconds
Started	Aug 04 04:32:04 PM PDT 24
Finished	Aug 04 04:32:05 PM PDT 24
Peak memory	204248 kb
Host	smart-695f08a1-61c8-4777-9101-29d1c78f610a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204056458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3204056458
Directory	/workspace/14.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1562224355
Short name	T16
Test name
Test status
Simulation time	113269487 ps
CPU time	2.09 seconds
Started	Aug 04 04:32:10 PM PDT 24
Finished	Aug 04 04:32:12 PM PDT 24
Peak memory	204420 kb
Host	smart-1432899c-8a0f-4773-8a38-993e18e26838
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562224355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1562224355
Directory	/workspace/11.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_intr_test.690803548
Short name	T32
Test name
Test status
Simulation time	51143276 ps
CPU time	0.68 seconds
Started	Aug 04 04:31:44 PM PDT 24
Finished	Aug 04 04:31:45 PM PDT 24
Peak memory	204192 kb
Host	smart-e4509525-1498-4a41-a825-a0861ae2f90f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690803548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.690803548
Directory	/workspace/2.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2182733675
Short name	T24
Test name
Test status
Simulation time	54775818 ps
CPU time	0.72 seconds
Started	Aug 04 04:31:53 PM PDT 24
Finished	Aug 04 04:31:54 PM PDT 24
Peak memory	204404 kb
Host	smart-2b947c23-041d-4f93-be9b-aa607981f486
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182733675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2182733675
Directory	/workspace/8.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3385344731
Short name	T23
Test name
Test status
Simulation time	119235996 ps
CPU time	2.57 seconds
Started	Aug 04 04:31:32 PM PDT 24
Finished	Aug 04 04:31:34 PM PDT 24
Peak memory	204428 kb
Host	smart-a496431f-d796-4ccb-9a4e-932d60e82b22
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385344731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3385344731
Directory	/workspace/0.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_intr_test.924274630
Short name	T79
Test name
Test status
Simulation time	16277611 ps
CPU time	0.69 seconds
Started	Aug 04 04:31:54 PM PDT 24
Finished	Aug 04 04:31:55 PM PDT 24
Peak memory	204248 kb
Host	smart-264ea37e-d82c-4817-8f48-5536234fbf4c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924274630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.924274630
Directory	/workspace/4.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4026609964
Short name	T9
Test name
Test status
Simulation time	25638024 ps
CPU time	0.79 seconds
Started	Aug 04 04:31:46 PM PDT 24
Finished	Aug 04 04:31:47 PM PDT 24
Peak memory	204316 kb
Host	smart-ccac6bfd-0781-43e3-9e9e-60f7684c5130
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026609964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.4026609964
Directory	/workspace/1.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2613101503
Short name	T26
Test name
Test status
Simulation time	108354354 ps
CPU time	1.16 seconds
Started	Aug 04 04:32:04 PM PDT 24
Finished	Aug 04 04:32:05 PM PDT 24
Peak memory	204468 kb
Host	smart-e24773aa-da99-4d49-9bff-c1322483cbd2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613101503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.2613101503
Directory	/workspace/6.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.3845470423
Short name	T39
Test name
Test status
Simulation time	95332265 ps
CPU time	0.68 seconds
Started	Aug 04 04:32:05 PM PDT 24
Finished	Aug 04 04:32:06 PM PDT 24
Peak memory	204280 kb
Host	smart-2986ce5a-2de6-4be7-87df-b35c9e41da53
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845470423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3845470423
Directory	/workspace/13.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/23.i2c_intr_test.2827289192
Short name	T82
Test name
Test status
Simulation time	31880331 ps
CPU time	0.67 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:07 PM PDT 24
Peak memory	204240 kb
Host	smart-1d907552-aa30-4b47-a701-27a0eb52f136
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827289192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2827289192
Directory	/workspace/23.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2936314288
Short name	T76
Test name
Test status
Simulation time	47884121 ps
CPU time	1.12 seconds
Started	Aug 04 04:31:51 PM PDT 24
Finished	Aug 04 04:31:53 PM PDT 24
Peak memory	204464 kb
Host	smart-b0bbefc1-aa5d-4ce0-8e32-50f4489e4799
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936314288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.2936314288
Directory	/workspace/7.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2451953707
Short name	T70
Test name
Test status
Simulation time	124838825 ps
CPU time	2.05 seconds
Started	Aug 04 04:31:39 PM PDT 24
Finished	Aug 04 04:31:41 PM PDT 24
Peak memory	204404 kb
Host	smart-c5531ba0-d8b6-49a9-903d-e4a37402ec5b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451953707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2451953707
Directory	/workspace/7.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.896909180
Short name	T66
Test name
Test status
Simulation time	126793941 ps
CPU time	2.26 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:08 PM PDT 24
Peak memory	204372 kb
Host	smart-342cdbc0-c7fd-456f-99f2-65833db5f388
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896909180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.896909180
Directory	/workspace/13.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.1010924461
Short name	T15
Test name
Test status
Simulation time	328207092 ps
CPU time	2.16 seconds
Started	Aug 04 04:31:58 PM PDT 24
Finished	Aug 04 04:32:01 PM PDT 24
Peak memory	204396 kb
Host	smart-42868822-a3bc-468a-9579-281d90518c7f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010924461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1010924461
Directory	/workspace/12.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_intr_test.3477645780
Short name	T49
Test name
Test status
Simulation time	47768251 ps
CPU time	0.67 seconds
Started	Aug 04 04:31:28 PM PDT 24
Finished	Aug 04 04:31:28 PM PDT 24
Peak memory	204568 kb
Host	smart-819ca4d9-0071-4192-8f5b-277f89297e32
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477645780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3477645780
Directory	/workspace/0.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3893931634
Short name	T50
Test name
Test status
Simulation time	80449139 ps
CPU time	1.24 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:08 PM PDT 24
Peak memory	204368 kb
Host	smart-8b4060ac-0bfa-4c91-8eb2-9403b94af6fa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893931634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o utstanding.3893931634
Directory	/workspace/14.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2987098778
Short name	T73
Test name
Test status
Simulation time	388449144 ps
CPU time	2.13 seconds
Started	Aug 04 04:32:07 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204436 kb
Host	smart-a119822c-fef1-45de-808b-97696918d72e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987098778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2987098778
Directory	/workspace/12.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.174597450
Short name	T53
Test name
Test status
Simulation time	116287120 ps
CPU time	2.18 seconds
Started	Aug 04 04:32:00 PM PDT 24
Finished	Aug 04 04:32:02 PM PDT 24
Peak memory	204480 kb
Host	smart-1ceac323-5368-4f91-ba71-38460154861b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174597450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.174597450
Directory	/workspace/0.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1127688000
Short name	T45
Test name
Test status
Simulation time	48980389 ps
CPU time	0.65 seconds
Started	Aug 04 04:31:21 PM PDT 24
Finished	Aug 04 04:31:23 PM PDT 24
Peak memory	204320 kb
Host	smart-a800a70d-74b7-49a4-bec3-7d8659c756e7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127688000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1127688000
Directory	/workspace/0.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2417543863
Short name	T95
Test name
Test status
Simulation time	25542241 ps
CPU time	1.22 seconds
Started	Aug 04 04:31:35 PM PDT 24
Finished	Aug 04 04:31:47 PM PDT 24
Peak memory	212704 kb
Host	smart-3be5dc49-eb44-42fb-ab8b-4e83bf9b29b6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417543863 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2417543863
Directory	/workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1413528792
Short name	T92
Test name
Test status
Simulation time	69583101 ps
CPU time	0.7 seconds
Started	Aug 04 04:31:35 PM PDT 24
Finished	Aug 04 04:31:36 PM PDT 24
Peak memory	204308 kb
Host	smart-e26c0f0b-b485-476a-97b0-68a4f9b72d12
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413528792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1413528792
Directory	/workspace/0.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2550590683
Short name	T56
Test name
Test status
Simulation time	192122654 ps
CPU time	0.85 seconds
Started	Aug 04 04:32:11 PM PDT 24
Finished	Aug 04 04:32:12 PM PDT 24
Peak memory	204368 kb
Host	smart-382b13af-c33f-4996-aa4a-5766e7b83c73
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550590683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou tstanding.2550590683
Directory	/workspace/0.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.432941846
Short name	T112
Test name
Test status
Simulation time	1399457036 ps
CPU time	1.86 seconds
Started	Aug 04 04:31:59 PM PDT 24
Finished	Aug 04 04:32:01 PM PDT 24
Peak memory	204564 kb
Host	smart-523c9415-f58c-47ac-acfb-2d1916312959
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432941846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.432941846
Directory	/workspace/0.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4087142405
Short name	T151
Test name
Test status
Simulation time	124400665 ps
CPU time	2.14 seconds
Started	Aug 04 04:31:52 PM PDT 24
Finished	Aug 04 04:31:54 PM PDT 24
Peak memory	204776 kb
Host	smart-6d1ec760-6778-452a-9d91-a53098ac1766
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087142405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.4087142405
Directory	/workspace/0.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1526038738
Short name	T38
Test name
Test status
Simulation time	89735863 ps
CPU time	1.19 seconds
Started	Aug 04 04:31:48 PM PDT 24
Finished	Aug 04 04:31:49 PM PDT 24
Peak memory	204380 kb
Host	smart-4350683e-bfe9-4b82-b8c6-58adbb79659c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526038738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1526038738
Directory	/workspace/1.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2277876102
Short name	T145
Test name
Test status
Simulation time	372718321 ps
CPU time	4.96 seconds
Started	Aug 04 04:31:54 PM PDT 24
Finished	Aug 04 04:31:59 PM PDT 24
Peak memory	204412 kb
Host	smart-b31fed2c-8341-436b-91fe-f7b312c2c697
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277876102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2277876102
Directory	/workspace/1.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1250480857
Short name	T94
Test name
Test status
Simulation time	32834686 ps
CPU time	0.93 seconds
Started	Aug 04 04:31:54 PM PDT 24
Finished	Aug 04 04:31:55 PM PDT 24
Peak memory	204316 kb
Host	smart-53c99080-f229-4900-9662-9c314bf9b686
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250480857 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1250480857
Directory	/workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.701494110
Short name	T42
Test name
Test status
Simulation time	50620158 ps
CPU time	0.76 seconds
Started	Aug 04 04:31:45 PM PDT 24
Finished	Aug 04 04:31:46 PM PDT 24
Peak memory	204412 kb
Host	smart-a017ad36-f318-4321-98f3-43a0a9f74c18
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701494110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.701494110
Directory	/workspace/1.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_intr_test.1044172116
Short name	T161
Test name
Test status
Simulation time	25041802 ps
CPU time	0.67 seconds
Started	Aug 04 04:31:46 PM PDT 24
Finished	Aug 04 04:31:47 PM PDT 24
Peak memory	204244 kb
Host	smart-1d470890-0d46-454a-93a1-856a311e7771
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044172116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1044172116
Directory	/workspace/1.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1549662876
Short name	T30
Test name
Test status
Simulation time	127174105 ps
CPU time	0.87 seconds
Started	Aug 04 04:31:46 PM PDT 24
Finished	Aug 04 04:31:47 PM PDT 24
Peak memory	204284 kb
Host	smart-948c61e9-7ad7-4e71-ac26-7dd0fba92acf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549662876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.1549662876
Directory	/workspace/1.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.4059409747
Short name	T89
Test name
Test status
Simulation time	25199730 ps
CPU time	1.36 seconds
Started	Aug 04 04:31:49 PM PDT 24
Finished	Aug 04 04:31:50 PM PDT 24
Peak memory	204492 kb
Host	smart-3b53213b-b5ca-445e-a2e7-dbb6b5f96f0c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059409747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.4059409747
Directory	/workspace/1.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3345421851
Short name	T5
Test name
Test status
Simulation time	646037430 ps
CPU time	1.36 seconds
Started	Aug 04 04:31:51 PM PDT 24
Finished	Aug 04 04:31:53 PM PDT 24
Peak memory	204512 kb
Host	smart-6754a7ff-6bb3-419c-b1d6-22f134f594ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345421851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3345421851
Directory	/workspace/1.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.451389127
Short name	T117
Test name
Test status
Simulation time	43143095 ps
CPU time	1.02 seconds
Started	Aug 04 04:31:53 PM PDT 24
Finished	Aug 04 04:31:55 PM PDT 24
Peak memory	204512 kb
Host	smart-b79f0d3d-7849-4976-ab37-d8ea460c7cfe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451389127 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.451389127
Directory	/workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1491673533
Short name	T115
Test name
Test status
Simulation time	71244173 ps
CPU time	0.72 seconds
Started	Aug 04 04:31:52 PM PDT 24
Finished	Aug 04 04:31:53 PM PDT 24
Peak memory	204276 kb
Host	smart-00c57a80-106b-4d1f-a082-29e473791573
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491673533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1491673533
Directory	/workspace/10.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_intr_test.1082764828
Short name	T90
Test name
Test status
Simulation time	19748922 ps
CPU time	0.69 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:07 PM PDT 24
Peak memory	204236 kb
Host	smart-09c7a64b-c6b2-4467-9157-79a61e1f63c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082764828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1082764828
Directory	/workspace/10.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.438446164
Short name	T131
Test name
Test status
Simulation time	145981764 ps
CPU time	0.87 seconds
Started	Aug 04 04:31:52 PM PDT 24
Finished	Aug 04 04:31:53 PM PDT 24
Peak memory	204312 kb
Host	smart-3484356e-5aef-4186-abcd-19cd466b0b0b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438446164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou tstanding.438446164
Directory	/workspace/10.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.880805592
Short name	T127
Test name
Test status
Simulation time	98553332 ps
CPU time	2.32 seconds
Started	Aug 04 04:32:00 PM PDT 24
Finished	Aug 04 04:32:03 PM PDT 24
Peak memory	204436 kb
Host	smart-b0fadf26-0e75-4588-b039-136906901898
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880805592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.880805592
Directory	/workspace/10.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2129539766
Short name	T121
Test name
Test status
Simulation time	82920014 ps
CPU time	1.4 seconds
Started	Aug 04 04:31:56 PM PDT 24
Finished	Aug 04 04:31:57 PM PDT 24
Peak memory	204364 kb
Host	smart-30284edb-c7c2-4b60-af93-6459ccc09f07
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129539766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2129539766
Directory	/workspace/10.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2706524590
Short name	T31
Test name
Test status
Simulation time	27217483 ps
CPU time	1.1 seconds
Started	Aug 04 04:31:57 PM PDT 24
Finished	Aug 04 04:31:58 PM PDT 24
Peak memory	212876 kb
Host	smart-402a6a13-382d-47aa-aec9-981da6431d89
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706524590 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2706524590
Directory	/workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.4230965968
Short name	T105
Test name
Test status
Simulation time	24765044 ps
CPU time	0.68 seconds
Started	Aug 04 04:32:02 PM PDT 24
Finished	Aug 04 04:32:03 PM PDT 24
Peak memory	204248 kb
Host	smart-835be6d5-999f-4d23-b53c-374067227377
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230965968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.4230965968
Directory	/workspace/11.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_intr_test.3575141562
Short name	T107
Test name
Test status
Simulation time	16401368 ps
CPU time	0.66 seconds
Started	Aug 04 04:31:41 PM PDT 24
Finished	Aug 04 04:31:41 PM PDT 24
Peak memory	204124 kb
Host	smart-eeb77ade-e821-4a5c-9803-3f84bbe90dc4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575141562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3575141562
Directory	/workspace/11.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3091813117
Short name	T102
Test name
Test status
Simulation time	88815095 ps
CPU time	1.11 seconds
Started	Aug 04 04:31:46 PM PDT 24
Finished	Aug 04 04:31:47 PM PDT 24
Peak memory	204548 kb
Host	smart-9adf9fac-c0e8-4061-bfd3-0faa3850fc38
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091813117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.3091813117
Directory	/workspace/11.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.158162666
Short name	T2
Test name
Test status
Simulation time	409901352 ps
CPU time	1.42 seconds
Started	Aug 04 04:32:00 PM PDT 24
Finished	Aug 04 04:32:01 PM PDT 24
Peak memory	204436 kb
Host	smart-da00da82-dfbf-4159-9f6b-58a68e76e47a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158162666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.158162666
Directory	/workspace/11.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1801995551
Short name	T20
Test name
Test status
Simulation time	71240659 ps
CPU time	0.97 seconds
Started	Aug 04 04:31:59 PM PDT 24
Finished	Aug 04 04:32:00 PM PDT 24
Peak memory	204392 kb
Host	smart-34f16485-5c6a-4e69-976d-5b8b0d264ecb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801995551 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1801995551
Directory	/workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.943473269
Short name	T8
Test name
Test status
Simulation time	26271623 ps
CPU time	0.67 seconds
Started	Aug 04 04:32:12 PM PDT 24
Finished	Aug 04 04:32:13 PM PDT 24
Peak memory	204312 kb
Host	smart-f0f9739b-b844-4338-83f9-7aab9b86d9ac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943473269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.943473269
Directory	/workspace/12.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_intr_test.3391067579
Short name	T34
Test name
Test status
Simulation time	44968662 ps
CPU time	0.63 seconds
Started	Aug 04 04:32:13 PM PDT 24
Finished	Aug 04 04:32:13 PM PDT 24
Peak memory	204208 kb
Host	smart-3abe64d0-f5b2-4b63-859a-3b726df13297
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391067579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3391067579
Directory	/workspace/12.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2341109739
Short name	T113
Test name
Test status
Simulation time	129169709 ps
CPU time	0.99 seconds
Started	Aug 04 04:32:12 PM PDT 24
Finished	Aug 04 04:32:13 PM PDT 24
Peak memory	204500 kb
Host	smart-54500f1e-5c67-4e36-b299-79f6bd81160a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341109739 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2341109739
Directory	/workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_intr_test.2253482226
Short name	T130
Test name
Test status
Simulation time	26975943 ps
CPU time	0.67 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:07 PM PDT 24
Peak memory	204252 kb
Host	smart-9b9e3893-3f76-4f06-871b-d8b0cf041eb7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253482226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2253482226
Directory	/workspace/13.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3721638482
Short name	T55
Test name
Test status
Simulation time	62328863 ps
CPU time	0.86 seconds
Started	Aug 04 04:32:17 PM PDT 24
Finished	Aug 04 04:32:18 PM PDT 24
Peak memory	204388 kb
Host	smart-9dee4625-8f19-4074-b82b-7867078eac63
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721638482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.3721638482
Directory	/workspace/13.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.2550367068
Short name	T125
Test name
Test status
Simulation time	63860311 ps
CPU time	1.57 seconds
Started	Aug 04 04:32:04 PM PDT 24
Finished	Aug 04 04:32:06 PM PDT 24
Peak memory	204396 kb
Host	smart-d3fdf937-99c1-4f45-925e-427649562334
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550367068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2550367068
Directory	/workspace/13.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.696963615
Short name	T123
Test name
Test status
Simulation time	39963905 ps
CPU time	1.09 seconds
Started	Aug 04 04:32:12 PM PDT 24
Finished	Aug 04 04:32:13 PM PDT 24
Peak memory	204528 kb
Host	smart-3e53d032-b46f-4b7b-9e16-e49c16e65dde
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696963615 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.696963615
Directory	/workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.92115379
Short name	T58
Test name
Test status
Simulation time	100826097 ps
CPU time	0.71 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204296 kb
Host	smart-6a56ac05-a14a-4077-8782-4d62bb4f25fe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92115379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.92115379
Directory	/workspace/14.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.1329043425
Short name	T144
Test name
Test status
Simulation time	168371862 ps
CPU time	2.89 seconds
Started	Aug 04 04:32:03 PM PDT 24
Finished	Aug 04 04:32:06 PM PDT 24
Peak memory	204472 kb
Host	smart-afd5937d-f1b8-4627-b650-a0156e1b699c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329043425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1329043425
Directory	/workspace/14.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2811424559
Short name	T69
Test name
Test status
Simulation time	228725922 ps
CPU time	2.14 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:08 PM PDT 24
Peak memory	204380 kb
Host	smart-478194e4-362e-46a8-8600-03f03ad6f968
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811424559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2811424559
Directory	/workspace/14.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.638534806
Short name	T137
Test name
Test status
Simulation time	41671153 ps
CPU time	1.24 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:10 PM PDT 24
Peak memory	212704 kb
Host	smart-6f880f03-5798-46cf-a9ae-41916d608ee4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638534806 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.638534806
Directory	/workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2005907769
Short name	T154
Test name
Test status
Simulation time	31367534 ps
CPU time	0.69 seconds
Started	Aug 04 04:32:04 PM PDT 24
Finished	Aug 04 04:32:05 PM PDT 24
Peak memory	204348 kb
Host	smart-e61c8a96-b475-478c-b762-73bf0a70356a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005907769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2005907769
Directory	/workspace/15.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_intr_test.852134099
Short name	T59
Test name
Test status
Simulation time	17204496 ps
CPU time	0.71 seconds
Started	Aug 04 04:32:02 PM PDT 24
Finished	Aug 04 04:32:02 PM PDT 24
Peak memory	204244 kb
Host	smart-a10698f7-e421-4ddd-aa48-3dc30c4c55f2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852134099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.852134099
Directory	/workspace/15.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2808330150
Short name	T75
Test name
Test status
Simulation time	73848246 ps
CPU time	0.83 seconds
Started	Aug 04 04:32:04 PM PDT 24
Finished	Aug 04 04:32:05 PM PDT 24
Peak memory	204416 kb
Host	smart-0d90e286-eea1-4eaf-a960-52f90533bf77
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808330150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.2808330150
Directory	/workspace/15.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.3076131591
Short name	T108
Test name
Test status
Simulation time	297497741 ps
CPU time	1.65 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:08 PM PDT 24
Peak memory	204568 kb
Host	smart-6cfe89d6-286e-4268-b739-00a105891ff8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076131591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3076131591
Directory	/workspace/15.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2497869229
Short name	T18
Test name
Test status
Simulation time	83595854 ps
CPU time	2.16 seconds
Started	Aug 04 04:32:01 PM PDT 24
Finished	Aug 04 04:32:03 PM PDT 24
Peak memory	204368 kb
Host	smart-902c7011-a968-455c-9608-9faa67a16a3f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497869229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2497869229
Directory	/workspace/15.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1714995690
Short name	T83
Test name
Test status
Simulation time	25988602 ps
CPU time	0.98 seconds
Started	Aug 04 04:32:03 PM PDT 24
Finished	Aug 04 04:32:04 PM PDT 24
Peak memory	204356 kb
Host	smart-772d2b61-428d-4100-9be4-49baeb9b1f9c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714995690 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1714995690
Directory	/workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2308153386
Short name	T62
Test name
Test status
Simulation time	46532267 ps
CPU time	0.68 seconds
Started	Aug 04 04:32:10 PM PDT 24
Finished	Aug 04 04:32:11 PM PDT 24
Peak memory	204312 kb
Host	smart-9ceb4185-e9ca-4cd6-881c-9081737d9d71
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308153386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2308153386
Directory	/workspace/16.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_intr_test.4233773874
Short name	T159
Test name
Test status
Simulation time	18505002 ps
CPU time	0.71 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204308 kb
Host	smart-41fe4e6b-7d3f-4d53-971e-548a63a1066c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233773874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.4233773874
Directory	/workspace/16.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.839567968
Short name	T78
Test name
Test status
Simulation time	55145553 ps
CPU time	1.12 seconds
Started	Aug 04 04:31:57 PM PDT 24
Finished	Aug 04 04:31:58 PM PDT 24
Peak memory	204424 kb
Host	smart-04642ee9-6f80-4ea0-be0a-685e4cb15e71
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839567968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou tstanding.839567968
Directory	/workspace/16.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.1929328344
Short name	T152
Test name
Test status
Simulation time	211010766 ps
CPU time	2.31 seconds
Started	Aug 04 04:32:10 PM PDT 24
Finished	Aug 04 04:32:13 PM PDT 24
Peak memory	204460 kb
Host	smart-1e888617-7ffd-42d9-8318-7b02dfe12b95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929328344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1929328344
Directory	/workspace/16.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1347601260
Short name	T164
Test name
Test status
Simulation time	83853118 ps
CPU time	1.27 seconds
Started	Aug 04 04:31:55 PM PDT 24
Finished	Aug 04 04:31:56 PM PDT 24
Peak memory	204428 kb
Host	smart-cd5aacbc-fe66-4ced-8c28-3a6ea7cec296
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347601260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1347601260
Directory	/workspace/16.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1024010131
Short name	T110
Test name
Test status
Simulation time	26081532 ps
CPU time	0.83 seconds
Started	Aug 04 04:32:10 PM PDT 24
Finished	Aug 04 04:32:11 PM PDT 24
Peak memory	204340 kb
Host	smart-104c35da-0cc6-4b58-9b71-3187ca314059
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024010131 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1024010131
Directory	/workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.2173516341
Short name	T40
Test name
Test status
Simulation time	250087750 ps
CPU time	0.74 seconds
Started	Aug 04 04:32:09 PM PDT 24
Finished	Aug 04 04:32:10 PM PDT 24
Peak memory	204312 kb
Host	smart-d36e1976-1301-4665-9798-980a3be2eee4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173516341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2173516341
Directory	/workspace/17.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_intr_test.1425742100
Short name	T148
Test name
Test status
Simulation time	34941919 ps
CPU time	0.7 seconds
Started	Aug 04 04:31:53 PM PDT 24
Finished	Aug 04 04:31:54 PM PDT 24
Peak memory	204588 kb
Host	smart-6d446630-8f25-48bf-93bf-77eda45955cc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425742100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1425742100
Directory	/workspace/17.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.173587787
Short name	T114
Test name
Test status
Simulation time	63987150 ps
CPU time	0.85 seconds
Started	Aug 04 04:32:13 PM PDT 24
Finished	Aug 04 04:32:14 PM PDT 24
Peak memory	204368 kb
Host	smart-02396940-191a-46ad-9277-a81a2af78931
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173587787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou tstanding.173587787
Directory	/workspace/17.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2813458080
Short name	T109
Test name
Test status
Simulation time	74705544 ps
CPU time	1.69 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204492 kb
Host	smart-25799d2c-2af4-4a7d-8b2d-fd7b453bfc20
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813458080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2813458080
Directory	/workspace/17.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.687080134
Short name	T19
Test name
Test status
Simulation time	97528425 ps
CPU time	2.13 seconds
Started	Aug 04 04:32:04 PM PDT 24
Finished	Aug 04 04:32:06 PM PDT 24
Peak memory	204436 kb
Host	smart-b8899e86-dae7-4d36-ad8b-c4461b69fa56
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687080134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.687080134
Directory	/workspace/17.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2036298134
Short name	T103
Test name
Test status
Simulation time	25385133 ps
CPU time	1.01 seconds
Started	Aug 04 04:32:00 PM PDT 24
Finished	Aug 04 04:32:01 PM PDT 24
Peak memory	204424 kb
Host	smart-3ef512c8-b995-48c3-a1fb-8f9e034f19c7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036298134 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2036298134
Directory	/workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.2267064166
Short name	T7
Test name
Test status
Simulation time	16441088 ps
CPU time	0.67 seconds
Started	Aug 04 04:32:09 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204264 kb
Host	smart-f9f5d9d9-eafe-4ac0-9dc4-9c4675d4356f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267064166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2267064166
Directory	/workspace/18.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_intr_test.292622117
Short name	T143
Test name
Test status
Simulation time	33261333 ps
CPU time	0.69 seconds
Started	Aug 04 04:32:01 PM PDT 24
Finished	Aug 04 04:32:02 PM PDT 24
Peak memory	204212 kb
Host	smart-490fcc74-6817-4b7a-9e0e-ec47f7252388
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292622117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.292622117
Directory	/workspace/18.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2779692009
Short name	T74
Test name
Test status
Simulation time	329102049 ps
CPU time	1 seconds
Started	Aug 04 04:32:11 PM PDT 24
Finished	Aug 04 04:32:12 PM PDT 24
Peak memory	204416 kb
Host	smart-ef4845f4-6aa3-48f4-881a-bb0dbbbdb7e7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779692009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.2779692009
Directory	/workspace/18.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2926450913
Short name	T85
Test name
Test status
Simulation time	106667570 ps
CPU time	1.57 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:10 PM PDT 24
Peak memory	204516 kb
Host	smart-0159d9fe-9f3c-47d3-9f8a-7af263d6f9cc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926450913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2926450913
Directory	/workspace/18.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2976355494
Short name	T118
Test name
Test status
Simulation time	158305090 ps
CPU time	1.48 seconds
Started	Aug 04 04:32:09 PM PDT 24
Finished	Aug 04 04:32:11 PM PDT 24
Peak memory	204484 kb
Host	smart-22ab492b-718f-4a8a-a4cd-acb60bdd36fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976355494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2976355494
Directory	/workspace/18.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2967104853
Short name	T98
Test name
Test status
Simulation time	121322622 ps
CPU time	1.03 seconds
Started	Aug 04 04:32:02 PM PDT 24
Finished	Aug 04 04:32:03 PM PDT 24
Peak memory	204408 kb
Host	smart-5853cb25-8222-4729-8a3e-96e169d8227a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967104853 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2967104853
Directory	/workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.845479792
Short name	T44
Test name
Test status
Simulation time	25849702 ps
CPU time	0.72 seconds
Started	Aug 04 04:31:55 PM PDT 24
Finished	Aug 04 04:31:56 PM PDT 24
Peak memory	204256 kb
Host	smart-89a4b3e3-3615-4c38-b369-b3609abacce1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845479792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.845479792
Directory	/workspace/19.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_intr_test.2861780718
Short name	T33
Test name
Test status
Simulation time	17248333 ps
CPU time	0.7 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:07 PM PDT 24
Peak memory	204184 kb
Host	smart-d04de6c6-a2de-4486-b781-a55faad25a25
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861780718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2861780718
Directory	/workspace/19.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3783688772
Short name	T129
Test name
Test status
Simulation time	65454263 ps
CPU time	0.85 seconds
Started	Aug 04 04:31:56 PM PDT 24
Finished	Aug 04 04:31:57 PM PDT 24
Peak memory	204312 kb
Host	smart-3c09f844-14e3-4e54-8624-6fb6885add1d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783688772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.3783688772
Directory	/workspace/19.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.2353345769
Short name	T22
Test name
Test status
Simulation time	669650104 ps
CPU time	2.24 seconds
Started	Aug 04 04:32:14 PM PDT 24
Finished	Aug 04 04:32:17 PM PDT 24
Peak memory	204444 kb
Host	smart-4ff655bf-6d77-441d-8d3b-ed703ce24895
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353345769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2353345769
Directory	/workspace/19.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.371591993
Short name	T48
Test name
Test status
Simulation time	53591668 ps
CPU time	1.4 seconds
Started	Aug 04 04:32:05 PM PDT 24
Finished	Aug 04 04:32:07 PM PDT 24
Peak memory	204388 kb
Host	smart-970cda3c-d01b-4374-968b-114cc3cf25e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371591993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.371591993
Directory	/workspace/19.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1789678250
Short name	T27
Test name
Test status
Simulation time	117694883 ps
CPU time	1.16 seconds
Started	Aug 04 04:31:39 PM PDT 24
Finished	Aug 04 04:31:40 PM PDT 24
Peak memory	204524 kb
Host	smart-07ab61b2-5852-4855-be0f-e409cfc35212
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789678250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1789678250
Directory	/workspace/2.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.517702863
Short name	T135
Test name
Test status
Simulation time	355453555 ps
CPU time	2.8 seconds
Started	Aug 04 04:31:54 PM PDT 24
Finished	Aug 04 04:31:57 PM PDT 24
Peak memory	204336 kb
Host	smart-eaed3769-53d6-4837-bb8f-6496f26a944e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517702863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.517702863
Directory	/workspace/2.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2535520794
Short name	T52
Test name
Test status
Simulation time	24956308 ps
CPU time	0.76 seconds
Started	Aug 04 04:31:36 PM PDT 24
Finished	Aug 04 04:31:37 PM PDT 24
Peak memory	204328 kb
Host	smart-c23fc3fc-52af-4deb-a619-50a55e934a64
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535520794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2535520794
Directory	/workspace/2.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.227877491
Short name	T37
Test name
Test status
Simulation time	28494646 ps
CPU time	0.78 seconds
Started	Aug 04 04:31:38 PM PDT 24
Finished	Aug 04 04:31:39 PM PDT 24
Peak memory	204332 kb
Host	smart-0e63b072-9929-453e-9f89-57d31bbbb6ff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227877491 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.227877491
Directory	/workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2726920378
Short name	T126
Test name
Test status
Simulation time	27790898 ps
CPU time	0.76 seconds
Started	Aug 04 04:31:28 PM PDT 24
Finished	Aug 04 04:31:29 PM PDT 24
Peak memory	204216 kb
Host	smart-5ce9afb3-d824-463d-ba24-3dc37491f6ae
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726920378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2726920378
Directory	/workspace/2.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2782839557
Short name	T119
Test name
Test status
Simulation time	69331512 ps
CPU time	0.84 seconds
Started	Aug 04 04:32:09 PM PDT 24
Finished	Aug 04 04:32:10 PM PDT 24
Peak memory	204312 kb
Host	smart-6de1cd02-f09f-4619-9114-6822099dc142
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782839557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.2782839557
Directory	/workspace/2.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.2222541407
Short name	T139
Test name
Test status
Simulation time	33233811 ps
CPU time	1.51 seconds
Started	Aug 04 04:31:59 PM PDT 24
Finished	Aug 04 04:32:01 PM PDT 24
Peak memory	204492 kb
Host	smart-a4028bff-1486-4a2f-9b4a-f888050db666
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222541407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2222541407
Directory	/workspace/2.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3583577419
Short name	T71
Test name
Test status
Simulation time	141659681 ps
CPU time	1.27 seconds
Started	Aug 04 04:32:04 PM PDT 24
Finished	Aug 04 04:32:05 PM PDT 24
Peak memory	204412 kb
Host	smart-b3b921ef-194b-4395-b40b-45a93858f883
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583577419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3583577419
Directory	/workspace/2.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.i2c_intr_test.1590024302
Short name	T153
Test name
Test status
Simulation time	18463840 ps
CPU time	0.74 seconds
Started	Aug 04 04:32:19 PM PDT 24
Finished	Aug 04 04:32:20 PM PDT 24
Peak memory	204208 kb
Host	smart-65e139da-4f23-4f31-a7e2-f0a4e74b3620
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590024302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1590024302
Directory	/workspace/20.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.i2c_intr_test.464260806
Short name	T158
Test name
Test status
Simulation time	46350062 ps
CPU time	0.66 seconds
Started	Aug 04 04:32:11 PM PDT 24
Finished	Aug 04 04:32:12 PM PDT 24
Peak memory	204188 kb
Host	smart-55bbdf58-1dbf-4895-84c7-8b3f65dc1ecc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464260806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.464260806
Directory	/workspace/21.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.i2c_intr_test.3972170429
Short name	T81
Test name
Test status
Simulation time	41633312 ps
CPU time	0.66 seconds
Started	Aug 04 04:32:13 PM PDT 24
Finished	Aug 04 04:32:13 PM PDT 24
Peak memory	204160 kb
Host	smart-fdb20166-90f4-4b1f-8f3c-6faa2c5bc019
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972170429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3972170429
Directory	/workspace/22.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.i2c_intr_test.3800834038
Short name	T36
Test name
Test status
Simulation time	30393821 ps
CPU time	0.68 seconds
Started	Aug 04 04:31:59 PM PDT 24
Finished	Aug 04 04:32:00 PM PDT 24
Peak memory	204196 kb
Host	smart-4bbdaafb-f970-4166-946c-1e1b249ee7e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800834038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3800834038
Directory	/workspace/24.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.i2c_intr_test.315971902
Short name	T46
Test name
Test status
Simulation time	70828779 ps
CPU time	0.66 seconds
Started	Aug 04 04:32:16 PM PDT 24
Finished	Aug 04 04:32:16 PM PDT 24
Peak memory	204168 kb
Host	smart-3953f271-df1d-46bf-a5f4-06f16ebda88b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315971902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.315971902
Directory	/workspace/25.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.i2c_intr_test.4060424384
Short name	T84
Test name
Test status
Simulation time	43989366 ps
CPU time	0.65 seconds
Started	Aug 04 04:32:17 PM PDT 24
Finished	Aug 04 04:32:18 PM PDT 24
Peak memory	204196 kb
Host	smart-8e10a2e7-fc61-4212-9757-b34ac7de2dbd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060424384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.4060424384
Directory	/workspace/26.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.i2c_intr_test.1900338656
Short name	T138
Test name
Test status
Simulation time	29836576 ps
CPU time	0.68 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:07 PM PDT 24
Peak memory	204200 kb
Host	smart-11f210be-de7c-4e03-9fc4-54e913f6e911
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900338656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1900338656
Directory	/workspace/27.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.i2c_intr_test.2312840976
Short name	T133
Test name
Test status
Simulation time	19146138 ps
CPU time	0.67 seconds
Started	Aug 04 04:32:03 PM PDT 24
Finished	Aug 04 04:32:04 PM PDT 24
Peak memory	204216 kb
Host	smart-6295c350-84a9-40f5-ac6e-3ca08a48563a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312840976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2312840976
Directory	/workspace/28.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.i2c_intr_test.1271711189
Short name	T10
Test name
Test status
Simulation time	30337049 ps
CPU time	0.63 seconds
Started	Aug 04 04:32:13 PM PDT 24
Finished	Aug 04 04:32:14 PM PDT 24
Peak memory	204192 kb
Host	smart-e8e2bc9d-d55c-4939-b103-ff36c9807c96
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271711189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1271711189
Directory	/workspace/29.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4182229496
Short name	T41
Test name
Test status
Simulation time	90037917 ps
CPU time	1.18 seconds
Started	Aug 04 04:31:54 PM PDT 24
Finished	Aug 04 04:31:55 PM PDT 24
Peak memory	204332 kb
Host	smart-edb2ca3e-591b-475b-96a0-b123adba3023
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182229496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.4182229496
Directory	/workspace/3.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2261979618
Short name	T155
Test name
Test status
Simulation time	121156679 ps
CPU time	2.5 seconds
Started	Aug 04 04:31:41 PM PDT 24
Finished	Aug 04 04:31:44 PM PDT 24
Peak memory	204380 kb
Host	smart-91bae2c1-1cb5-4243-92b8-7c7d66a6c3b7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261979618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2261979618
Directory	/workspace/3.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3596729433
Short name	T43
Test name
Test status
Simulation time	28408359 ps
CPU time	0.71 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204272 kb
Host	smart-d091de6c-ffc0-4775-bf1f-6d370ee3d549
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596729433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3596729433
Directory	/workspace/3.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.834092326
Short name	T21
Test name
Test status
Simulation time	53782492 ps
CPU time	1.22 seconds
Started	Aug 04 04:31:57 PM PDT 24
Finished	Aug 04 04:31:59 PM PDT 24
Peak memory	204532 kb
Host	smart-1e29eadd-0317-41f3-ade7-c18ac41a16c2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834092326 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.834092326
Directory	/workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.3258759043
Short name	T51
Test name
Test status
Simulation time	97678000 ps
CPU time	0.72 seconds
Started	Aug 04 04:31:34 PM PDT 24
Finished	Aug 04 04:31:34 PM PDT 24
Peak memory	204276 kb
Host	smart-6307e151-5491-47eb-a0d6-88cd71fe0794
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258759043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3258759043
Directory	/workspace/3.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_intr_test.305357407
Short name	T88
Test name
Test status
Simulation time	18623524 ps
CPU time	0.68 seconds
Started	Aug 04 04:31:41 PM PDT 24
Finished	Aug 04 04:31:42 PM PDT 24
Peak memory	204204 kb
Host	smart-64a9be46-757b-43f0-a3ef-a83a4e8dce62
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305357407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.305357407
Directory	/workspace/3.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2647004874
Short name	T77
Test name
Test status
Simulation time	225995613 ps
CPU time	1.14 seconds
Started	Aug 04 04:31:43 PM PDT 24
Finished	Aug 04 04:31:44 PM PDT 24
Peak memory	204452 kb
Host	smart-0763bb52-e73a-40c2-a5df-4874895538fd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647004874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou tstanding.2647004874
Directory	/workspace/3.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.2734379902
Short name	T101
Test name
Test status
Simulation time	81355023 ps
CPU time	1.42 seconds
Started	Aug 04 04:31:42 PM PDT 24
Finished	Aug 04 04:31:48 PM PDT 24
Peak memory	204460 kb
Host	smart-d5986991-44e4-4ba4-bdec-9f71c6a335a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734379902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2734379902
Directory	/workspace/3.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.i2c_intr_test.2455667269
Short name	T124
Test name
Test status
Simulation time	25187256 ps
CPU time	0.66 seconds
Started	Aug 04 04:32:13 PM PDT 24
Finished	Aug 04 04:32:14 PM PDT 24
Peak memory	204228 kb
Host	smart-46ed3412-095d-44a1-ad77-70a7d74fd437
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455667269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2455667269
Directory	/workspace/30.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.i2c_intr_test.3613468981
Short name	T47
Test name
Test status
Simulation time	22523933 ps
CPU time	0.63 seconds
Started	Aug 04 04:32:14 PM PDT 24
Finished	Aug 04 04:32:15 PM PDT 24
Peak memory	204192 kb
Host	smart-1fd052c5-f24b-4b14-ab03-b6bf11a57220
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613468981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3613468981
Directory	/workspace/31.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.i2c_intr_test.286502523
Short name	T134
Test name
Test status
Simulation time	15793957 ps
CPU time	0.67 seconds
Started	Aug 04 04:32:11 PM PDT 24
Finished	Aug 04 04:32:12 PM PDT 24
Peak memory	204188 kb
Host	smart-ed2b04ef-1e67-4480-a7d4-4775147d029a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286502523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.286502523
Directory	/workspace/32.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.i2c_intr_test.3993047520
Short name	T122
Test name
Test status
Simulation time	30533761 ps
CPU time	0.65 seconds
Started	Aug 04 04:32:11 PM PDT 24
Finished	Aug 04 04:32:11 PM PDT 24
Peak memory	204196 kb
Host	smart-120312aa-b541-4158-9db9-d44255a323a9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993047520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3993047520
Directory	/workspace/33.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.i2c_intr_test.2494184588
Short name	T136
Test name
Test status
Simulation time	16836753 ps
CPU time	0.64 seconds
Started	Aug 04 04:32:14 PM PDT 24
Finished	Aug 04 04:32:15 PM PDT 24
Peak memory	204244 kb
Host	smart-56aefcab-2fca-44c5-867a-82fb4af6dfd3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494184588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2494184588
Directory	/workspace/34.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.i2c_intr_test.2643924933
Short name	T11
Test name
Test status
Simulation time	18557067 ps
CPU time	0.64 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:07 PM PDT 24
Peak memory	204244 kb
Host	smart-95276988-764c-4e85-8b82-cc3d93f2e0db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643924933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2643924933
Directory	/workspace/35.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.i2c_intr_test.440741044
Short name	T140
Test name
Test status
Simulation time	35631976 ps
CPU time	0.73 seconds
Started	Aug 04 04:32:03 PM PDT 24
Finished	Aug 04 04:32:04 PM PDT 24
Peak memory	204588 kb
Host	smart-a58c7672-73ee-4971-80c4-e3c8922a61f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440741044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.440741044
Directory	/workspace/36.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.i2c_intr_test.4021532706
Short name	T97
Test name
Test status
Simulation time	16628916 ps
CPU time	0.67 seconds
Started	Aug 04 04:31:58 PM PDT 24
Finished	Aug 04 04:31:59 PM PDT 24
Peak memory	204248 kb
Host	smart-68787536-7a80-44ed-a17e-d699e7f144fd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021532706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.4021532706
Directory	/workspace/37.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.i2c_intr_test.446135248
Short name	T120
Test name
Test status
Simulation time	33437505 ps
CPU time	0.66 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204212 kb
Host	smart-d3650be3-be03-480b-96ac-59a891287812
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446135248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.446135248
Directory	/workspace/38.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.i2c_intr_test.1017954518
Short name	T63
Test name
Test status
Simulation time	17167911 ps
CPU time	0.64 seconds
Started	Aug 04 04:32:20 PM PDT 24
Finished	Aug 04 04:32:20 PM PDT 24
Peak memory	204224 kb
Host	smart-0be4b405-d993-4e6d-b709-85b2b977768c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017954518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1017954518
Directory	/workspace/39.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2207339110
Short name	T25
Test name
Test status
Simulation time	96499502 ps
CPU time	1.21 seconds
Started	Aug 04 04:31:50 PM PDT 24
Finished	Aug 04 04:31:51 PM PDT 24
Peak memory	204484 kb
Host	smart-b3ad141c-189f-4088-9535-2752a1fe8bf5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207339110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2207339110
Directory	/workspace/4.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3242603823
Short name	T54
Test name
Test status
Simulation time	513695712 ps
CPU time	4.48 seconds
Started	Aug 04 04:31:57 PM PDT 24
Finished	Aug 04 04:32:02 PM PDT 24
Peak memory	204404 kb
Host	smart-9ef85d26-af5f-4cd8-9bff-f7619af7ec65
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242603823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.3242603823
Directory	/workspace/4.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1873152427
Short name	T28
Test name
Test status
Simulation time	26047273 ps
CPU time	0.77 seconds
Started	Aug 04 04:31:59 PM PDT 24
Finished	Aug 04 04:32:00 PM PDT 24
Peak memory	204616 kb
Host	smart-2e1b22d7-04d8-422c-a8b6-4c0d422887d5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873152427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1873152427
Directory	/workspace/4.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1593196564
Short name	T142
Test name
Test status
Simulation time	39810619 ps
CPU time	0.95 seconds
Started	Aug 04 04:32:11 PM PDT 24
Finished	Aug 04 04:32:17 PM PDT 24
Peak memory	204352 kb
Host	smart-79a5b4dc-279d-4824-be7b-3649d7b645b7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593196564 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1593196564
Directory	/workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.1014381301
Short name	T99
Test name
Test status
Simulation time	29737085 ps
CPU time	0.74 seconds
Started	Aug 04 04:31:48 PM PDT 24
Finished	Aug 04 04:31:54 PM PDT 24
Peak memory	204336 kb
Host	smart-ccd7578b-2148-4066-90e8-7372055de02f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014381301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1014381301
Directory	/workspace/4.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3615537065
Short name	T57
Test name
Test status
Simulation time	79874746 ps
CPU time	0.86 seconds
Started	Aug 04 04:31:49 PM PDT 24
Finished	Aug 04 04:31:50 PM PDT 24
Peak memory	204316 kb
Host	smart-ff09a08d-adfb-43d3-845d-6f30ca8e20b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615537065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.3615537065
Directory	/workspace/4.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.277339630
Short name	T3
Test name
Test status
Simulation time	109002626 ps
CPU time	2.33 seconds
Started	Aug 04 04:31:44 PM PDT 24
Finished	Aug 04 04:31:46 PM PDT 24
Peak memory	204492 kb
Host	smart-2316442f-15bc-4f78-9995-d81a7001628e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277339630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.277339630
Directory	/workspace/4.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.623797482
Short name	T72
Test name
Test status
Simulation time	127821611 ps
CPU time	1.4 seconds
Started	Aug 04 04:31:40 PM PDT 24
Finished	Aug 04 04:31:42 PM PDT 24
Peak memory	204392 kb
Host	smart-e2a68433-ebf9-4644-bb30-03161e559d00
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623797482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.623797482
Directory	/workspace/4.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.i2c_intr_test.753485792
Short name	T12
Test name
Test status
Simulation time	47162482 ps
CPU time	0.66 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204260 kb
Host	smart-54154d6f-8726-4a6f-a8f5-0f9c026efc9f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753485792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.753485792
Directory	/workspace/40.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.i2c_intr_test.1211022475
Short name	T86
Test name
Test status
Simulation time	51187215 ps
CPU time	0.64 seconds
Started	Aug 04 04:32:12 PM PDT 24
Finished	Aug 04 04:32:13 PM PDT 24
Peak memory	204248 kb
Host	smart-34270b5f-6287-4771-91eb-346afa6c1392
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211022475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1211022475
Directory	/workspace/41.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.i2c_intr_test.1998927315
Short name	T65
Test name
Test status
Simulation time	31078822 ps
CPU time	0.64 seconds
Started	Aug 04 04:32:10 PM PDT 24
Finished	Aug 04 04:32:11 PM PDT 24
Peak memory	204248 kb
Host	smart-0473309e-a4fa-461e-821d-fdcfe2e092ed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998927315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1998927315
Directory	/workspace/42.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.i2c_intr_test.3241154814
Short name	T128
Test name
Test status
Simulation time	39397765 ps
CPU time	0.71 seconds
Started	Aug 04 04:32:14 PM PDT 24
Finished	Aug 04 04:32:15 PM PDT 24
Peak memory	204276 kb
Host	smart-0695ccbc-07db-4cd5-ad56-f3583eac88c2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241154814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3241154814
Directory	/workspace/43.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.i2c_intr_test.1373744924
Short name	T100
Test name
Test status
Simulation time	16669816 ps
CPU time	0.67 seconds
Started	Aug 04 04:31:59 PM PDT 24
Finished	Aug 04 04:32:00 PM PDT 24
Peak memory	204216 kb
Host	smart-c5db9da6-c369-4c65-aea0-3a24503db9c3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373744924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1373744924
Directory	/workspace/44.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.i2c_intr_test.3272337810
Short name	T157
Test name
Test status
Simulation time	20228084 ps
CPU time	0.7 seconds
Started	Aug 04 04:32:00 PM PDT 24
Finished	Aug 04 04:32:01 PM PDT 24
Peak memory	204236 kb
Host	smart-22db0976-a9c9-48a6-86ba-6de7eb9450a4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272337810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3272337810
Directory	/workspace/45.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.i2c_intr_test.4180482928
Short name	T150
Test name
Test status
Simulation time	21750810 ps
CPU time	0.68 seconds
Started	Aug 04 04:32:16 PM PDT 24
Finished	Aug 04 04:32:17 PM PDT 24
Peak memory	204236 kb
Host	smart-f6625742-3e4e-4326-9f14-35b567e0bbd1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180482928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.4180482928
Directory	/workspace/46.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.i2c_intr_test.3738314879
Short name	T96
Test name
Test status
Simulation time	38462729 ps
CPU time	0.66 seconds
Started	Aug 04 04:32:04 PM PDT 24
Finished	Aug 04 04:32:05 PM PDT 24
Peak memory	204236 kb
Host	smart-4872d418-df0f-4751-afe0-eea615d8bdb7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738314879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3738314879
Directory	/workspace/47.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.i2c_intr_test.3459664428
Short name	T146
Test name
Test status
Simulation time	16156464 ps
CPU time	0.65 seconds
Started	Aug 04 04:32:10 PM PDT 24
Finished	Aug 04 04:32:11 PM PDT 24
Peak memory	204196 kb
Host	smart-ea617b65-23a1-432c-b162-29ba0a0e9a6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459664428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3459664428
Directory	/workspace/48.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.i2c_intr_test.4088738984
Short name	T116
Test name
Test status
Simulation time	15377999 ps
CPU time	0.67 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204160 kb
Host	smart-7f27ac47-980a-4aae-8f93-b54353c485f0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088738984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.4088738984
Directory	/workspace/49.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.670420612
Short name	T17
Test name
Test status
Simulation time	29047793 ps
CPU time	0.8 seconds
Started	Aug 04 04:32:02 PM PDT 24
Finished	Aug 04 04:32:03 PM PDT 24
Peak memory	204324 kb
Host	smart-498dd4c2-aa30-4175-bfa4-adf525b68e58
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670420612 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.670420612
Directory	/workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.2176095905
Short name	T1
Test name
Test status
Simulation time	63134555 ps
CPU time	0.73 seconds
Started	Aug 04 04:31:38 PM PDT 24
Finished	Aug 04 04:31:39 PM PDT 24
Peak memory	204280 kb
Host	smart-0b59dac3-631d-46f8-a0cf-1753e01df8b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176095905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2176095905
Directory	/workspace/5.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_intr_test.2833273106
Short name	T64
Test name
Test status
Simulation time	53117082 ps
CPU time	0.63 seconds
Started	Aug 04 04:32:02 PM PDT 24
Finished	Aug 04 04:32:03 PM PDT 24
Peak memory	204324 kb
Host	smart-939b07d6-d8dc-4501-834b-688140ce78f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833273106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2833273106
Directory	/workspace/5.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2971886599
Short name	T93
Test name
Test status
Simulation time	69114008 ps
CPU time	0.85 seconds
Started	Aug 04 04:32:18 PM PDT 24
Finished	Aug 04 04:32:19 PM PDT 24
Peak memory	204272 kb
Host	smart-21727ff1-b184-4b7f-8390-4998a658dd42
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971886599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.2971886599
Directory	/workspace/5.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.946087737
Short name	T61
Test name
Test status
Simulation time	551528297 ps
CPU time	1.82 seconds
Started	Aug 04 04:31:37 PM PDT 24
Finished	Aug 04 04:31:39 PM PDT 24
Peak memory	204516 kb
Host	smart-e10ed1a1-5fd4-4786-9a43-eb49992d282f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946087737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.946087737
Directory	/workspace/5.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3060656729
Short name	T106
Test name
Test status
Simulation time	272764811 ps
CPU time	1.41 seconds
Started	Aug 04 04:31:29 PM PDT 24
Finished	Aug 04 04:31:30 PM PDT 24
Peak memory	204320 kb
Host	smart-ac59b6e9-6e30-4c16-af74-8202415c249d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060656729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3060656729
Directory	/workspace/5.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.130634652
Short name	T132
Test name
Test status
Simulation time	35637769 ps
CPU time	0.96 seconds
Started	Aug 04 04:31:49 PM PDT 24
Finished	Aug 04 04:31:50 PM PDT 24
Peak memory	204352 kb
Host	smart-c8edc722-c2de-4f7a-9013-64aff1acb68a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130634652 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.130634652
Directory	/workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.1182365860
Short name	T147
Test name
Test status
Simulation time	24158493 ps
CPU time	0.67 seconds
Started	Aug 04 04:31:58 PM PDT 24
Finished	Aug 04 04:31:59 PM PDT 24
Peak memory	204288 kb
Host	smart-db0e8e1f-41d1-4a2e-86ad-471738884bfc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182365860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1182365860
Directory	/workspace/6.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_intr_test.2398468262
Short name	T160
Test name
Test status
Simulation time	43078199 ps
CPU time	0.66 seconds
Started	Aug 04 04:31:46 PM PDT 24
Finished	Aug 04 04:31:47 PM PDT 24
Peak memory	204220 kb
Host	smart-06b70c22-c18a-4dd3-af24-3b10bde65a74
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398468262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2398468262
Directory	/workspace/6.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.3976063451
Short name	T6
Test name
Test status
Simulation time	126734745 ps
CPU time	1.71 seconds
Started	Aug 04 04:31:55 PM PDT 24
Finished	Aug 04 04:31:56 PM PDT 24
Peak memory	204492 kb
Host	smart-64292657-70e6-44f7-959c-69c89627e8d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976063451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3976063451
Directory	/workspace/6.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1905549799
Short name	T68
Test name
Test status
Simulation time	458959214 ps
CPU time	1.37 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:07 PM PDT 24
Peak memory	204544 kb
Host	smart-cdb8c74f-0f5b-4202-88e8-078da234895c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905549799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1905549799
Directory	/workspace/6.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1428193212
Short name	T163
Test name
Test status
Simulation time	113084268 ps
CPU time	0.79 seconds
Started	Aug 04 04:31:42 PM PDT 24
Finished	Aug 04 04:31:43 PM PDT 24
Peak memory	204388 kb
Host	smart-2c9063f1-0ab3-4b83-925f-3e3b61c56a5c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428193212 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1428193212
Directory	/workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3677739463
Short name	T162
Test name
Test status
Simulation time	21635183 ps
CPU time	0.69 seconds
Started	Aug 04 04:32:04 PM PDT 24
Finished	Aug 04 04:32:05 PM PDT 24
Peak memory	204252 kb
Host	smart-5bbb6bc0-4310-4687-846f-d5b4ccd1ad58
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677739463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3677739463
Directory	/workspace/7.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_intr_test.637156408
Short name	T80
Test name
Test status
Simulation time	31824554 ps
CPU time	0.63 seconds
Started	Aug 04 04:31:46 PM PDT 24
Finished	Aug 04 04:31:46 PM PDT 24
Peak memory	204220 kb
Host	smart-ca7280c4-1d4f-4d54-ba30-70b7b7fcc610
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637156408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.637156408
Directory	/workspace/7.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.4100156233
Short name	T14
Test name
Test status
Simulation time	62247359 ps
CPU time	1.56 seconds
Started	Aug 04 04:32:12 PM PDT 24
Finished	Aug 04 04:32:13 PM PDT 24
Peak memory	204816 kb
Host	smart-651b085f-a5f2-4428-a521-285cd525225e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100156233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.4100156233
Directory	/workspace/7.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1378722203
Short name	T91
Test name
Test status
Simulation time	93116295 ps
CPU time	0.86 seconds
Started	Aug 04 04:32:00 PM PDT 24
Finished	Aug 04 04:32:01 PM PDT 24
Peak memory	204344 kb
Host	smart-3f457fa0-220c-4898-8e77-c117ac30a64a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378722203 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1378722203
Directory	/workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_intr_test.165548784
Short name	T104
Test name
Test status
Simulation time	136423540 ps
CPU time	0.62 seconds
Started	Aug 04 04:31:52 PM PDT 24
Finished	Aug 04 04:31:53 PM PDT 24
Peak memory	204216 kb
Host	smart-2a262245-2d6b-4140-ae07-9ff654e871f0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165548784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.165548784
Directory	/workspace/8.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2763203091
Short name	T156
Test name
Test status
Simulation time	40184787 ps
CPU time	0.85 seconds
Started	Aug 04 04:32:14 PM PDT 24
Finished	Aug 04 04:32:14 PM PDT 24
Peak memory	204284 kb
Host	smart-696d6e99-98ac-4206-8e68-1f9686cecffa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763203091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.2763203091
Directory	/workspace/8.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.170028311
Short name	T141
Test name
Test status
Simulation time	59957271 ps
CPU time	1.35 seconds
Started	Aug 04 04:31:58 PM PDT 24
Finished	Aug 04 04:32:00 PM PDT 24
Peak memory	204528 kb
Host	smart-da67ee5c-284d-4039-b68c-c2910d1523e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170028311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.170028311
Directory	/workspace/8.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4002385949
Short name	T35
Test name
Test status
Simulation time	86884836 ps
CPU time	2.08 seconds
Started	Aug 04 04:32:06 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204456 kb
Host	smart-eacd472f-8fd0-4fb9-868a-342ea621c439
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002385949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.4002385949
Directory	/workspace/8.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.279777841
Short name	T87
Test name
Test status
Simulation time	53174549 ps
CPU time	0.91 seconds
Started	Aug 04 04:31:57 PM PDT 24
Finished	Aug 04 04:31:58 PM PDT 24
Peak memory	204372 kb
Host	smart-841d39d2-6593-48c7-bb04-db2290a51a29
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279777841 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.279777841
Directory	/workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.278540776
Short name	T29
Test name
Test status
Simulation time	19468057 ps
CPU time	0.78 seconds
Started	Aug 04 04:32:00 PM PDT 24
Finished	Aug 04 04:32:01 PM PDT 24
Peak memory	204300 kb
Host	smart-b7183743-c72c-488f-a3ec-5575de2030d4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278540776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.278540776
Directory	/workspace/9.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_intr_test.1828484607
Short name	T149
Test name
Test status
Simulation time	18801448 ps
CPU time	0.66 seconds
Started	Aug 04 04:31:48 PM PDT 24
Finished	Aug 04 04:31:49 PM PDT 24
Peak memory	204220 kb
Host	smart-53a89363-4b4e-4f59-8f45-1c624ba75476
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828484607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1828484607
Directory	/workspace/9.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1114674183
Short name	T111
Test name
Test status
Simulation time	54926985 ps
CPU time	0.88 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:09 PM PDT 24
Peak memory	204656 kb
Host	smart-ceefa09e-76ff-42e0-9d24-952db218244a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114674183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.1114674183
Directory	/workspace/9.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3691206177
Short name	T60
Test name
Test status
Simulation time	389032441 ps
CPU time	2.02 seconds
Started	Aug 04 04:32:04 PM PDT 24
Finished	Aug 04 04:32:06 PM PDT 24
Peak memory	204456 kb
Host	smart-218f988d-cf54-4c64-b5b1-036f37e4df0b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691206177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3691206177
Directory	/workspace/9.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1613354039
Short name	T67
Test name
Test status
Simulation time	465536127 ps
CPU time	2.07 seconds
Started	Aug 04 04:32:08 PM PDT 24
Finished	Aug 04 04:32:11 PM PDT 24
Peak memory	204372 kb
Host	smart-71e25a66-49d7-4699-bc92-922a2cbf4ab1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613354039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1613354039
Directory	/workspace/9.i2c_tl_intg_err/latest