Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1			T12	4		T10	4		T11	7
all_values[1]	266	1			T12	4		T10	4		T11	7
all_values[2]	266	1			T12	4		T10	4		T11	7
all_values[3]	266	1			T12	4		T10	4		T11	7
all_values[4]	266	1			T12	4		T10	4		T11	7
all_values[5]	266	1			T12	4		T10	4		T11	7
all_values[6]	266	1			T12	4		T10	4		T11	7
all_values[7]	266	1			T12	4		T10	4		T11	7
all_values[8]	266	1			T12	4		T10	4		T11	7
all_values[9]	266	1			T12	4		T10	4		T11	7
all_values[10]	266	1			T12	4		T10	4		T11	7
all_values[11]	266	1			T12	4		T10	4		T11	7
all_values[12]	266	1			T12	4		T10	4		T11	7
all_values[13]	266	1			T12	4		T10	4		T11	7
all_values[14]	266	1			T12	4		T10	4		T11	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2185

1

T12

29

T10

39

T11

49

auto[1]

1805

1

T12

31

T10

21

T11

56

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

731

1

T12

8

T10

12

T11

12

auto[1]

3259

1

T12

52

T10

48

T11

93

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2371

1

T12

35

T10

34

T11

59

auto[1]

1619

1

T12

25

T10

26

T11

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	34	1			T12	1		T11	3		T59	3
all_values[0]	auto[0]	auto[0]	auto[1]	55	1			T10	1		T11	1		T13	1
all_values[0]	auto[0]	auto[1]	auto[0]	26	1			T12	3		T59	2		T79	2
all_values[0]	auto[0]	auto[1]	auto[1]	48	1			T13	1		T64	2		T63	1
all_values[0]	auto[1]	auto[0]	auto[1]	50	1			T10	3		T11	1		T13	3
all_values[0]	auto[1]	auto[1]	auto[1]	53	1			T11	2		T13	2		T59	1
all_values[1]	auto[0]	auto[0]	auto[0]	22	1			T13	1		T59	1		T33	1
all_values[1]	auto[0]	auto[0]	auto[1]	63	1			T12	1		T11	2		T13	3
all_values[1]	auto[0]	auto[1]	auto[0]	12	1			T79	2		T80	1		T81	1
all_values[1]	auto[0]	auto[1]	auto[1]	54	1			T12	2		T10	1		T11	2
all_values[1]	auto[1]	auto[0]	auto[1]	63	1			T12	1		T10	2		T11	1
all_values[1]	auto[1]	auto[1]	auto[1]	52	1			T10	1		T11	2		T59	1
all_values[2]	auto[0]	auto[0]	auto[0]	40	1			T12	1		T11	2		T59	4
all_values[2]	auto[0]	auto[0]	auto[1]	47	1			T12	1		T11	1		T13	2
all_values[2]	auto[0]	auto[1]	auto[0]	23	1			T11	1		T59	1		T64	1
all_values[2]	auto[0]	auto[1]	auto[1]	51	1			T10	2		T13	2		T59	1
all_values[2]	auto[1]	auto[0]	auto[1]	68	1			T12	1		T10	2		T11	2
all_values[2]	auto[1]	auto[1]	auto[1]	37	1			T12	1		T11	1		T13	1
all_values[3]	auto[0]	auto[0]	auto[0]	29	1			T10	2		T63	2		T32	1
all_values[3]	auto[0]	auto[0]	auto[1]	54	1			T10	1		T11	2		T59	3
all_values[3]	auto[0]	auto[1]	auto[0]	21	1			T12	1		T79	1		T36	1
all_values[3]	auto[0]	auto[1]	auto[1]	51	1			T12	1		T11	1		T13	1
all_values[3]	auto[1]	auto[0]	auto[1]	62	1			T11	4		T13	1		T59	4
all_values[3]	auto[1]	auto[1]	auto[1]	49	1			T12	2		T10	1		T13	5
all_values[4]	auto[0]	auto[0]	auto[0]	26	1			T13	1		T59	2		T63	1
all_values[4]	auto[0]	auto[0]	auto[1]	56	1			T12	1		T10	1		T11	1
all_values[4]	auto[0]	auto[1]	auto[0]	21	1			T13	1		T63	1		T79	1
all_values[4]	auto[0]	auto[1]	auto[1]	48	1			T12	1		T10	1		T11	2
all_values[4]	auto[1]	auto[0]	auto[1]	66	1			T12	2		T10	2		T13	1
all_values[4]	auto[1]	auto[1]	auto[1]	49	1			T11	4		T13	1		T64	1
all_values[5]	auto[0]	auto[0]	auto[0]	16	1			T10	1		T11	1		T34	1
all_values[5]	auto[0]	auto[0]	auto[1]	62	1			T12	1		T11	1		T13	1
all_values[5]	auto[0]	auto[1]	auto[0]	9	1			T11	2		T79	2		T81	1
all_values[5]	auto[0]	auto[1]	auto[1]	53	1			T10	1		T11	1		T59	1
all_values[5]	auto[1]	auto[0]	auto[1]	76	1			T12	2		T10	1		T11	2
all_values[5]	auto[1]	auto[1]	auto[1]	50	1			T12	1		T10	1		T13	2
all_values[6]	auto[0]	auto[0]	auto[0]	41	1			T10	1		T11	1		T13	2
all_values[6]	auto[0]	auto[0]	auto[1]	50	1			T10	1		T11	3		T13	2
all_values[6]	auto[0]	auto[1]	auto[0]	27	1			T79	2		T33	1		T46	3
all_values[6]	auto[0]	auto[1]	auto[1]	58	1			T12	3		T10	1		T11	1
all_values[6]	auto[1]	auto[0]	auto[1]	55	1			T11	2		T13	2		T64	3
all_values[6]	auto[1]	auto[1]	auto[1]	35	1			T12	1		T10	1		T59	1
all_values[7]	auto[0]	auto[0]	auto[0]	30	1			T10	1		T13	1		T79	2
all_values[7]	auto[0]	auto[0]	auto[1]	52	1			T12	2		T10	1		T11	3
all_values[7]	auto[0]	auto[1]	auto[0]	19	1			T11	1		T13	1		T59	2
all_values[7]	auto[0]	auto[1]	auto[1]	51	1			T10	1		T11	1		T13	1
all_values[7]	auto[1]	auto[0]	auto[1]	56	1			T12	1		T13	3		T64	2
all_values[7]	auto[1]	auto[1]	auto[1]	58	1			T12	1		T10	1		T11	2
all_values[8]	auto[0]	auto[0]	auto[0]	27	1			T10	1		T13	4		T64	2
all_values[8]	auto[0]	auto[0]	auto[1]	61	1			T12	1		T10	1		T11	4
all_values[8]	auto[0]	auto[1]	auto[0]	19	1			T12	1		T13	1		T59	2
all_values[8]	auto[0]	auto[1]	auto[1]	53	1			T11	2		T59	2		T63	3
all_values[8]	auto[1]	auto[0]	auto[1]	60	1			T12	2		T10	1		T13	1
all_values[8]	auto[1]	auto[1]	auto[1]	46	1			T10	1		T11	1		T65	1
all_values[9]	auto[0]	auto[0]	auto[0]	27	1			T10	3		T13	1		T59	2
all_values[9]	auto[0]	auto[0]	auto[1]	62	1			T11	2		T13	2		T59	3
all_values[9]	auto[0]	auto[1]	auto[0]	21	1			T10	1		T34	1		T46	2
all_values[9]	auto[0]	auto[1]	auto[1]	39	1			T12	2		T11	1		T13	1
all_values[9]	auto[1]	auto[0]	auto[1]	75	1			T12	1		T11	3		T13	3
all_values[9]	auto[1]	auto[1]	auto[1]	42	1			T12	1		T11	1		T59	1
all_values[10]	auto[0]	auto[0]	auto[0]	28	1			T13	1		T64	2		T65	1
all_values[10]	auto[0]	auto[0]	auto[1]	57	1			T12	2		T10	1		T11	1
all_values[10]	auto[0]	auto[1]	auto[0]	20	1			T59	3		T79	2		T33	1
all_values[10]	auto[0]	auto[1]	auto[1]	56	1			T12	1		T10	1		T11	2
all_values[10]	auto[1]	auto[0]	auto[1]	46	1			T12	1		T10	2		T11	1
all_values[10]	auto[1]	auto[1]	auto[1]	59	1			T11	3		T13	1		T64	1
all_values[11]	auto[0]	auto[0]	auto[0]	24	1			T13	2		T64	1		T34	1
all_values[11]	auto[0]	auto[0]	auto[1]	51	1			T12	2		T11	1		T13	2
all_values[11]	auto[0]	auto[1]	auto[0]	9	1			T59	1		T46	2		T82	1
all_values[11]	auto[0]	auto[1]	auto[1]	69	1			T10	1		T11	1		T59	3
all_values[11]	auto[1]	auto[0]	auto[1]	62	1			T12	2		T10	1		T13	2
all_values[11]	auto[1]	auto[1]	auto[1]	51	1			T10	2		T11	5		T13	1
all_values[12]	auto[0]	auto[0]	auto[0]	27	1			T10	2		T64	1		T65	2
all_values[12]	auto[0]	auto[0]	auto[1]	58	1			T12	2		T10	1		T11	1
all_values[12]	auto[0]	auto[1]	auto[0]	16	1			T11	1		T59	2		T79	1
all_values[12]	auto[0]	auto[1]	auto[1]	59	1			T12	1		T11	3		T13	2
all_values[12]	auto[1]	auto[0]	auto[1]	52	1			T13	1		T59	2		T65	1
all_values[12]	auto[1]	auto[1]	auto[1]	54	1			T12	1		T10	1		T11	2
all_values[13]	auto[0]	auto[0]	auto[0]	29	1			T59	1		T64	1		T65	1
all_values[13]	auto[0]	auto[0]	auto[1]	59	1			T10	1		T11	1		T13	3
all_values[13]	auto[0]	auto[1]	auto[0]	31	1			T12	1		T79	1		T32	2
all_values[13]	auto[0]	auto[1]	auto[1]	48	1			T12	1		T10	1		T11	3
all_values[13]	auto[1]	auto[0]	auto[1]	59	1			T12	1		T10	2		T11	2
all_values[13]	auto[1]	auto[1]	auto[1]	40	1			T12	1		T11	1		T13	1
all_values[14]	auto[0]	auto[0]	auto[0]	37	1			T13	2		T64	2		T65	4
all_values[14]	auto[0]	auto[0]	auto[1]	59	1			T10	2		T13	1		T59	3
all_values[14]	auto[0]	auto[1]	auto[0]	20	1			T64	2		T80	1		T47	1
all_values[14]	auto[0]	auto[1]	auto[1]	56	1			T12	2		T10	1		T11	3
all_values[14]	auto[1]	auto[0]	auto[1]	52	1			T10	1		T13	1		T59	2
all_values[14]	auto[1]	auto[1]	auto[1]	42	1			T12	2		T11	4		T13	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal