Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	802612	1			T1	1		T2	2		T3	1
all_values[1]	802612	1			T1	1		T2	2		T3	1
all_values[2]	802612	1			T1	1		T2	2		T3	1
all_values[3]	802612	1			T1	1		T2	2		T3	1
all_values[4]	802612	1			T1	1		T2	2		T3	1
all_values[5]	802612	1			T1	1		T2	2		T3	1
all_values[6]	802612	1			T1	1		T2	2		T3	1
all_values[7]	802612	1			T1	1		T2	2		T3	1
all_values[8]	802612	1			T1	1		T2	2		T3	1
all_values[9]	802612	1			T1	1		T2	2		T3	1
all_values[10]	802612	1			T1	1		T2	2		T3	1
all_values[11]	802612	1			T1	1		T2	2		T3	1
all_values[12]	802612	1			T1	1		T2	2		T3	1
all_values[13]	802612	1			T1	1		T2	2		T3	1
all_values[14]	802612	1			T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9874829

1

T1

15

T2

24

T3

15

auto[1]

2164351

1

T2

6

T4

2

T5

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11686782

1

T1

15

T2

30

T3

15

auto[1]

352398

1

T21

197

T29

447

T109

8310

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100485	1			T1	1		T3	1		T7	405
all_values[0]	auto[0]	auto[1]	4456	1			T21	9		T29	21		T109	14
all_values[0]	auto[1]	auto[0]	678651	1			T2	2		T4	1		T5	4
all_values[0]	auto[1]	auto[1]	19020	1			T21	4		T29	10		T109	625
all_values[1]	auto[0]	auto[0]	778555	1			T1	1		T2	2		T3	1
all_values[1]	auto[0]	auto[1]	23539	1			T21	7		T29	27		T33	3
all_values[1]	auto[1]	auto[0]	384	1			T269	10		T270	19		T271	2
all_values[1]	auto[1]	auto[1]	134	1			T21	7		T29	4		T33	4
all_values[2]	auto[0]	auto[0]	778097	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	24172	1			T21	9		T29	27		T109	633
all_values[2]	auto[1]	auto[0]	195	1			T2	1		T48	2		T58	1
all_values[2]	auto[1]	auto[1]	148	1			T21	4		T29	4		T109	5
all_values[3]	auto[0]	auto[0]	784290	1			T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	18164	1			T21	7		T29	20		T109	633
all_values[3]	auto[1]	auto[1]	158	1			T21	7		T29	6		T109	4
all_values[4]	auto[0]	auto[0]	778261	1			T1	1		T2	2		T3	1
all_values[4]	auto[0]	auto[1]	24181	1			T21	9		T29	24		T109	637
all_values[4]	auto[1]	auto[0]	9	1			T25	2		T26	1		T30	1
all_values[4]	auto[1]	auto[1]	161	1			T21	5		T29	7		T109	2
all_values[5]	auto[0]	auto[0]	780626	1			T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	21823	1			T21	5		T29	22		T109	638
all_values[5]	auto[1]	auto[1]	163	1			T21	9		T29	8		T109	1
all_values[6]	auto[0]	auto[0]	778281	1			T1	1		T2	2		T3	1
all_values[6]	auto[0]	auto[1]	24149	1			T21	10		T29	26		T109	634
all_values[6]	auto[1]	auto[1]	182	1			T21	3		T29	4		T109	5
all_values[7]	auto[0]	auto[0]	749482	1			T1	1		T2	2		T3	1
all_values[7]	auto[0]	auto[1]	23235	1			T21	11		T29	23		T109	608
all_values[7]	auto[1]	auto[0]	28803	1			T7	123		T15	1		T18	4
all_values[7]	auto[1]	auto[1]	1092	1			T21	2		T29	7		T109	30
all_values[8]	auto[0]	auto[0]	778310	1			T1	1		T2	2		T3	1
all_values[8]	auto[0]	auto[1]	24145	1			T21	10		T29	22		T109	635
all_values[8]	auto[1]	auto[1]	157	1			T21	4		T29	7		T109	4
all_values[9]	auto[0]	auto[0]	163398	1			T1	1		T2	2		T3	1
all_values[9]	auto[0]	auto[1]	4643	1			T21	4		T29	23		T109	613
all_values[9]	auto[1]	auto[0]	615750	1			T5	1		T7	8		T48	1
all_values[9]	auto[1]	auto[1]	18821	1			T21	10		T29	7		T109	26
all_values[10]	auto[0]	auto[0]	778933	1			T1	1		T2	2		T3	1
all_values[10]	auto[0]	auto[1]	23533	1			T21	10		T29	25		T109	8
all_values[10]	auto[1]	auto[1]	146	1			T21	4		T29	6		T109	1
all_values[11]	auto[0]	auto[0]	2493	1			T1	1		T3	1		T7	2
all_values[11]	auto[0]	auto[1]	299	1			T21	8		T29	18		T109	8
all_values[11]	auto[1]	auto[0]	775794	1			T2	2		T4	1		T5	4
all_values[11]	auto[1]	auto[1]	24026	1			T21	6		T29	12		T109	630
all_values[12]	auto[0]	auto[0]	778219	1			T1	1		T2	1		T3	1
all_values[12]	auto[0]	auto[1]	24178	1			T21	9		T29	23		T109	634
all_values[12]	auto[1]	auto[0]	67	1			T2	1		T58	1		T57	1
all_values[12]	auto[1]	auto[1]	148	1			T21	3		T29	3		T109	5
all_values[13]	auto[0]	auto[0]	778571	1			T1	1		T2	2		T3	1
all_values[13]	auto[0]	auto[1]	23876	1			T21	4		T29	23		T109	634
all_values[13]	auto[1]	auto[1]	165	1			T21	5		T29	7		T109	5
all_values[14]	auto[0]	auto[0]	779128	1			T1	1		T2	2		T3	1
all_values[14]	auto[0]	auto[1]	23307	1			T21	9		T29	24		T109	633
all_values[14]	auto[1]	auto[1]	177	1			T21	3		T29	7		T109	5