Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	802612	1			T1	1		T2	2		T3	1
all_pins[1]	802612	1			T1	1		T2	2		T3	1
all_pins[2]	802612	1			T1	1		T2	2		T3	1
all_pins[3]	802612	1			T1	1		T2	2		T3	1
all_pins[4]	802612	1			T1	1		T2	2		T3	1
all_pins[5]	802612	1			T1	1		T2	2		T3	1
all_pins[6]	802612	1			T1	1		T2	2		T3	1
all_pins[7]	802612	1			T1	1		T2	2		T3	1
all_pins[8]	802612	1			T1	1		T2	2		T3	1
all_pins[9]	802612	1			T1	1		T2	2		T3	1
all_pins[10]	802612	1			T1	1		T2	2		T3	1
all_pins[11]	802612	1			T1	1		T2	2		T3	1
all_pins[12]	802612	1			T1	1		T2	2		T3	1
all_pins[13]	802612	1			T1	1		T2	2		T3	1
all_pins[14]	802612	1			T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9880790	1			T1	15		T2	27		T3	15
values[0x1]	2158390	1			T2	3		T4	2		T5	9
transitions[0x0=>0x1]	2157618	1			T2	3		T4	2		T5	9
transitions[0x1=>0x0]	2156309	1			T2	3		T4	1		T5	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	108582	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	694030	1			T2	1		T4	1		T5	4
all_pins[0]	transitions[0x0=>0x1]	693561	1			T2	1		T4	1		T5	4
all_pins[0]	transitions[0x1=>0x0]	63	1			T21	2		T29	1		T175	15
all_pins[1]	values[0x0]	802080	1			T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	532	1			T269	14		T270	24		T271	2
all_pins[1]	transitions[0x0=>0x1]	518	1			T269	14		T270	24		T271	2
all_pins[1]	transitions[0x1=>0x0]	110	1			T58	1		T278	1		T279	1
all_pins[2]	values[0x0]	802488	1			T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	124	1			T58	1		T278	1		T279	1
all_pins[2]	transitions[0x0=>0x1]	115	1			T58	1		T278	1		T279	1
all_pins[2]	transitions[0x1=>0x0]	64	1			T21	4		T29	2		T109	2
all_pins[3]	values[0x0]	802539	1			T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	73	1			T21	5		T29	2		T109	2
all_pins[3]	transitions[0x0=>0x1]	62	1			T21	4		T29	1		T109	2
all_pins[3]	transitions[0x1=>0x0]	81	1			T25	2		T26	1		T30	1
all_pins[4]	values[0x0]	802520	1			T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	92	1			T25	2		T26	1		T30	1
all_pins[4]	transitions[0x0=>0x1]	73	1			T25	2		T26	1		T30	1
all_pins[4]	transitions[0x1=>0x0]	64	1			T21	2		T29	2		T33	2
all_pins[5]	values[0x0]	802529	1			T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	83	1			T21	5		T29	2		T109	1
all_pins[5]	transitions[0x0=>0x1]	57	1			T21	4		T29	1		T33	3
all_pins[5]	transitions[0x1=>0x0]	67	1			T29	1		T109	3		T280	1
all_pins[6]	values[0x0]	802519	1			T1	1		T2	2		T3	1
all_pins[6]	values[0x1]	93	1			T21	1		T29	2		T109	4
all_pins[6]	transitions[0x0=>0x1]	61	1			T21	1		T29	2		T109	4
all_pins[6]	transitions[0x1=>0x0]	32474	1			T7	131		T15	1		T18	4
all_pins[7]	values[0x0]	770106	1			T1	1		T2	2		T3	1
all_pins[7]	values[0x1]	32506	1			T7	131		T15	1		T18	4
all_pins[7]	transitions[0x0=>0x1]	32480	1			T7	131		T15	1		T18	4
all_pins[7]	transitions[0x1=>0x0]	57	1			T21	1		T29	4		T33	2
all_pins[8]	values[0x0]	802529	1			T1	1		T2	2		T3	1
all_pins[8]	values[0x1]	83	1			T21	3		T29	6		T33	2
all_pins[8]	transitions[0x0=>0x1]	62	1			T21	3		T29	6		T33	2
all_pins[8]	transitions[0x1=>0x0]	634485	1			T5	1		T7	8		T48	1
all_pins[9]	values[0x0]	168106	1			T1	1		T2	2		T3	1
all_pins[9]	values[0x1]	634506	1			T5	1		T7	8		T48	1
all_pins[9]	transitions[0x0=>0x1]	634488	1			T5	1		T7	8		T48	1
all_pins[9]	transitions[0x1=>0x0]	48	1			T21	1		T29	1		T33	1
all_pins[10]	values[0x0]	802546	1			T1	1		T2	2		T3	1
all_pins[10]	values[0x1]	66	1			T21	1		T29	2		T33	1
all_pins[10]	transitions[0x0=>0x1]	47	1			T21	1		T29	2		T33	1
all_pins[10]	transitions[0x1=>0x0]	795868	1			T2	1		T4	1		T5	4
all_pins[11]	values[0x0]	6725	1			T1	1		T2	1		T3	1
all_pins[11]	values[0x1]	795887	1			T2	1		T4	1		T5	4
all_pins[11]	transitions[0x0=>0x1]	795852	1			T2	1		T4	1		T5	4
all_pins[11]	transitions[0x1=>0x0]	100	1			T2	1		T57	1		T74	1
all_pins[12]	values[0x0]	802477	1			T1	1		T2	1		T3	1
all_pins[12]	values[0x1]	135	1			T2	1		T58	1		T57	1
all_pins[12]	transitions[0x0=>0x1]	123	1			T2	1		T58	1		T57	1
all_pins[12]	transitions[0x1=>0x0]	71	1			T21	5		T29	3		T109	3
all_pins[13]	values[0x0]	802529	1			T1	1		T2	2		T3	1
all_pins[13]	values[0x1]	83	1			T21	5		T29	3		T109	5
all_pins[13]	transitions[0x0=>0x1]	63	1			T21	5		T29	2		T109	2
all_pins[13]	transitions[0x1=>0x0]	77	1			T21	1		T29	6		T33	1
all_pins[14]	values[0x0]	802515	1			T1	1		T2	2		T3	1
all_pins[14]	values[0x1]	97	1			T21	1		T29	7		T109	3
all_pins[14]	transitions[0x0=>0x1]	56	1			T29	6		T109	1		T239	1
all_pins[14]	transitions[0x1=>0x0]	692680	1			T2	1		T5	3		T6	1