Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	375	1			T21	11		T29	12		T109	8
all_values[1]	375	1			T21	11		T29	12		T109	8
all_values[2]	375	1			T21	11		T29	12		T109	8
all_values[3]	375	1			T21	11		T29	12		T109	8
all_values[4]	375	1			T21	11		T29	12		T109	8
all_values[5]	375	1			T21	11		T29	12		T109	8
all_values[6]	375	1			T21	11		T29	12		T109	8
all_values[7]	375	1			T21	11		T29	12		T109	8
all_values[8]	375	1			T21	11		T29	12		T109	8
all_values[9]	375	1			T21	11		T29	12		T109	8
all_values[10]	375	1			T21	11		T29	12		T109	8
all_values[11]	375	1			T21	11		T29	12		T109	8
all_values[12]	375	1			T21	11		T29	12		T109	8
all_values[13]	375	1			T21	11		T29	12		T109	8
all_values[14]	375	1			T21	11		T29	12		T109	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3007

1

T21

71

T29

90

T109

60

auto[1]

2618

1

T21

94

T29

90

T109

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

992

1

T21

13

T29

16

T109

18

auto[1]

4633

1

T21

152

T29

164

T109

102

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3356

1

T21

104

T29

106

T109

69

auto[1]

2269

1

T21

61

T29

74

T109

51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	35	1			T280	2		T239	1		T281	2
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T21	3		T29	5		T109	2
all_values[0]	auto[0]	auto[1]	auto[0]	19	1			T21	1		T280	2		T282	1
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T21	3		T29	2		T109	2
all_values[0]	auto[1]	auto[0]	auto[1]	77	1			T21	1		T29	3		T109	2
all_values[0]	auto[1]	auto[1]	auto[1]	88	1			T21	3		T29	2		T109	2
all_values[1]	auto[0]	auto[0]	auto[0]	43	1			T109	2		T33	2		T280	1
all_values[1]	auto[0]	auto[0]	auto[1]	71	1			T21	1		T29	3		T280	1
all_values[1]	auto[0]	auto[1]	auto[0]	40	1			T109	6		T283	2		T127	2
all_values[1]	auto[0]	auto[1]	auto[1]	87	1			T21	3		T29	5		T33	1
all_values[1]	auto[1]	auto[0]	auto[1]	75	1			T21	4		T29	4		T33	4
all_values[1]	auto[1]	auto[1]	auto[1]	59	1			T21	3		T280	2		T125	2
all_values[2]	auto[0]	auto[0]	auto[0]	42	1			T33	1		T280	1		T125	1
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T21	3		T29	6		T109	1
all_values[2]	auto[0]	auto[1]	auto[0]	27	1			T21	1		T109	1		T125	2
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T21	3		T29	2		T109	1
all_values[2]	auto[1]	auto[0]	auto[1]	82	1			T21	1		T29	2		T109	5
all_values[2]	auto[1]	auto[1]	auto[1]	66	1			T21	3		T29	2		T33	2
all_values[3]	auto[0]	auto[0]	auto[0]	43	1			T29	1		T109	1		T33	1
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T21	1		T29	1		T109	2
all_values[3]	auto[0]	auto[1]	auto[0]	24	1			T29	3		T109	1		T33	2
all_values[3]	auto[0]	auto[1]	auto[1]	90	1			T21	6		T29	3		T109	2
all_values[3]	auto[1]	auto[0]	auto[1]	94	1			T21	2		T29	1		T109	1
all_values[3]	auto[1]	auto[1]	auto[1]	51	1			T21	2		T29	3		T109	1
all_values[4]	auto[0]	auto[0]	auto[0]	34	1			T33	1		T280	1		T284	1
all_values[4]	auto[0]	auto[0]	auto[1]	88	1			T21	2		T29	4		T109	5
all_values[4]	auto[0]	auto[1]	auto[0]	14	1			T280	1		T283	2		T285	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T21	4		T29	1		T109	1
all_values[4]	auto[1]	auto[0]	auto[1]	87	1			T21	2		T29	4		T109	1
all_values[4]	auto[1]	auto[1]	auto[1]	74	1			T21	3		T29	3		T109	1
all_values[5]	auto[0]	auto[0]	auto[0]	42	1			T280	4		T239	2		T125	3
all_values[5]	auto[0]	auto[0]	auto[1]	82	1			T21	1		T29	5		T109	4
all_values[5]	auto[0]	auto[1]	auto[0]	38	1			T29	1		T125	4		T238	1
all_values[5]	auto[0]	auto[1]	auto[1]	66	1			T21	5		T29	2		T109	1
all_values[5]	auto[1]	auto[0]	auto[1]	79	1			T21	2		T29	1		T33	5
all_values[5]	auto[1]	auto[1]	auto[1]	68	1			T21	3		T29	3		T109	3
all_values[6]	auto[0]	auto[0]	auto[0]	32	1			T21	1		T33	1		T283	2
all_values[6]	auto[0]	auto[0]	auto[1]	72	1			T21	2		T29	4		T109	1
all_values[6]	auto[0]	auto[1]	auto[0]	28	1			T29	1		T283	3		T286	1
all_values[6]	auto[0]	auto[1]	auto[1]	89	1			T21	5		T29	1		T109	3
all_values[6]	auto[1]	auto[0]	auto[1]	82	1			T21	2		T29	2		T109	1
all_values[6]	auto[1]	auto[1]	auto[1]	72	1			T21	1		T29	4		T109	3
all_values[7]	auto[0]	auto[0]	auto[0]	39	1			T21	1		T33	1		T280	1
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T21	7		T29	5		T109	3
all_values[7]	auto[0]	auto[1]	auto[0]	24	1			T29	1		T109	1		T33	1
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T21	1		T29	3		T109	1
all_values[7]	auto[1]	auto[0]	auto[1]	85	1			T29	2		T109	1		T33	3
all_values[7]	auto[1]	auto[1]	auto[1]	71	1			T21	2		T29	1		T109	2
all_values[8]	auto[0]	auto[0]	auto[0]	56	1			T29	1		T33	1		T280	1
all_values[8]	auto[0]	auto[0]	auto[1]	75	1			T21	4		T29	2		T109	2
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T29	1		T33	1		T125	1
all_values[8]	auto[0]	auto[1]	auto[1]	82	1			T21	4		T29	4		T109	3
all_values[8]	auto[1]	auto[0]	auto[1]	80	1			T21	1		T29	1		T109	2
all_values[8]	auto[1]	auto[1]	auto[1]	57	1			T21	2		T29	3		T109	1
all_values[9]	auto[0]	auto[0]	auto[0]	30	1			T33	1		T280	1		T238	1
all_values[9]	auto[0]	auto[0]	auto[1]	76	1			T21	4		T29	3		T109	3
all_values[9]	auto[0]	auto[1]	auto[0]	35	1			T29	1		T33	3		T280	3
all_values[9]	auto[0]	auto[1]	auto[1]	72	1			T21	1		T29	2		T239	1
all_values[9]	auto[1]	auto[0]	auto[1]	83	1			T21	3		T29	1		T109	1
all_values[9]	auto[1]	auto[1]	auto[1]	79	1			T21	3		T29	5		T109	4
all_values[10]	auto[0]	auto[0]	auto[0]	43	1			T109	2		T239	1		T283	1
all_values[10]	auto[0]	auto[0]	auto[1]	75	1			T21	5		T29	4		T33	4
all_values[10]	auto[0]	auto[1]	auto[0]	35	1			T109	2		T283	2		T281	2
all_values[10]	auto[0]	auto[1]	auto[1]	76	1			T21	2		T29	2		T109	3
all_values[10]	auto[1]	auto[0]	auto[1]	90	1			T21	3		T29	3		T109	1
all_values[10]	auto[1]	auto[1]	auto[1]	56	1			T21	1		T29	3		T239	2
all_values[11]	auto[0]	auto[0]	auto[0]	42	1			T29	1		T239	5		T281	1
all_values[11]	auto[0]	auto[0]	auto[1]	74	1			T21	1		T29	1		T109	1
all_values[11]	auto[0]	auto[1]	auto[0]	22	1			T109	1		T125	2		T286	1
all_values[11]	auto[0]	auto[1]	auto[1]	83	1			T21	4		T29	3		T109	1
all_values[11]	auto[1]	auto[0]	auto[1]	87	1			T21	2		T29	4		T109	2
all_values[11]	auto[1]	auto[1]	auto[1]	67	1			T21	4		T29	3		T109	3
all_values[12]	auto[0]	auto[0]	auto[0]	36	1			T21	1		T29	1		T33	1
all_values[12]	auto[0]	auto[0]	auto[1]	75	1			T21	1		T29	4		T109	2
all_values[12]	auto[0]	auto[1]	auto[0]	25	1			T21	1		T29	3		T239	1
all_values[12]	auto[0]	auto[1]	auto[1]	91	1			T21	5		T29	1		T109	1
all_values[12]	auto[1]	auto[0]	auto[1]	87	1			T21	2		T29	1		T109	4
all_values[12]	auto[1]	auto[1]	auto[1]	61	1			T21	1		T29	2		T109	1
all_values[13]	auto[0]	auto[0]	auto[0]	42	1			T21	2		T33	1		T280	1
all_values[13]	auto[0]	auto[0]	auto[1]	76	1			T21	1		T29	3		T280	1
all_values[13]	auto[0]	auto[1]	auto[0]	29	1			T21	3		T29	1		T125	1
all_values[13]	auto[0]	auto[1]	auto[1]	73	1			T21	2		T29	3		T109	2
all_values[13]	auto[1]	auto[0]	auto[1]	88	1			T21	1		T29	3		T109	2
all_values[13]	auto[1]	auto[1]	auto[1]	67	1			T21	2		T29	2		T109	4
all_values[14]	auto[0]	auto[0]	auto[0]	30	1			T280	3		T239	2		T281	1
all_values[14]	auto[0]	auto[0]	auto[1]	95	1			T21	3		T29	2		T109	3
all_values[14]	auto[0]	auto[1]	auto[0]	18	1			T21	2		T109	1		T280	1
all_values[14]	auto[0]	auto[1]	auto[1]	75	1			T21	4		T29	4		T109	1
all_values[14]	auto[1]	auto[0]	auto[1]	77	1			T21	1		T29	2		T109	3
all_values[14]	auto[1]	auto[1]	auto[1]	80	1			T21	1		T29	4		T33	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal