Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29185515	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8230789

1

T1

22

T2

3958

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36626169	1			T1	4		T2	15103		T3	14
values[0x0]	394367	1			T1	25		T2	93		T3	8
values[0x1]	395768	1			T1	28		T2	86		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20475297	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16941007

1

T1

31

T2

7283

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	132954	1			T1	56		T2	50		T4	174
valid_sources[0x01]	146488	1			T2	56		T4	207		T5	19
valid_sources[0x02]	134720	1			T2	65		T4	185		T5	18
valid_sources[0x03]	134899	1			T2	61		T4	199		T5	15
valid_sources[0x04]	165872	1			T2	58		T4	175		T5	22
valid_sources[0x05]	134357	1			T2	48		T4	193		T5	21
valid_sources[0x06]	142958	1			T2	53		T4	216		T5	21
valid_sources[0x07]	153878	1			T2	62		T4	209		T5	21
valid_sources[0x08]	143325	1			T2	70		T4	178		T5	25
valid_sources[0x09]	135487	1			T2	57		T4	147		T5	20
valid_sources[0x0a]	142842	1			T2	64		T4	170		T5	25
valid_sources[0x0b]	140258	1			T2	57		T4	197		T5	25
valid_sources[0x0c]	154505	1			T2	55		T4	176		T5	20
valid_sources[0x0d]	151086	1			T2	58		T4	199		T5	22
valid_sources[0x0e]	157307	1			T2	67		T4	183		T5	26
valid_sources[0x0f]	141411	1			T2	55		T4	201		T5	28
valid_sources[0x10]	133861	1			T2	49		T4	192		T5	20
valid_sources[0x11]	152199	1			T2	60		T4	187		T5	16
valid_sources[0x12]	139698	1			T2	53		T4	205		T5	22
valid_sources[0x13]	133729	1			T2	62		T4	186		T5	18
valid_sources[0x14]	142501	1			T2	49		T4	182		T5	27
valid_sources[0x15]	155931	1			T2	58		T4	181		T5	24
valid_sources[0x16]	157404	1			T2	82		T4	207		T5	24
valid_sources[0x17]	131232	1			T2	65		T4	176		T5	29
valid_sources[0x18]	138006	1			T2	77		T4	189		T5	15
valid_sources[0x19]	148425	1			T2	60		T4	176		T5	21
valid_sources[0x1a]	148008	1			T2	65		T4	164		T5	21
valid_sources[0x1b]	155748	1			T2	51		T4	227		T5	24
valid_sources[0x1c]	140280	1			T2	49		T4	173		T5	30
valid_sources[0x1d]	161729	1			T2	70		T4	215		T5	17
valid_sources[0x1e]	152283	1			T2	55		T4	209		T5	23
valid_sources[0x1f]	146139	1			T2	56		T4	178		T5	24
valid_sources[0x20]	179289	1			T2	53		T4	215		T5	27
valid_sources[0x21]	141370	1			T2	57		T4	208		T5	25
valid_sources[0x22]	138790	1			T2	61		T4	157		T5	27
valid_sources[0x23]	147405	1			T2	45		T4	192		T5	22
valid_sources[0x24]	138041	1			T2	65		T4	168		T5	18
valid_sources[0x25]	138272	1			T2	62		T4	193		T5	33
valid_sources[0x26]	149494	1			T2	69		T4	177		T5	22
valid_sources[0x27]	131299	1			T2	62		T4	169		T5	16
valid_sources[0x28]	148431	1			T2	45		T4	221		T5	23
valid_sources[0x29]	140954	1			T2	56		T4	216		T5	29
valid_sources[0x2a]	143975	1			T2	50		T4	189		T5	21
valid_sources[0x2b]	165651	1			T2	62		T4	153		T5	26
valid_sources[0x2c]	145721	1			T2	60		T4	207		T5	30
valid_sources[0x2d]	145414	1			T2	58		T4	191		T5	18
valid_sources[0x2e]	145762	1			T2	80		T4	217		T5	23
valid_sources[0x2f]	144256	1			T2	58		T4	228		T5	29
valid_sources[0x30]	157819	1			T2	58		T4	177		T5	18
valid_sources[0x31]	146392	1			T2	72		T4	177		T5	18
valid_sources[0x32]	126955	1			T2	57		T4	182		T5	25
valid_sources[0x33]	146928	1			T2	64		T4	191		T5	29
valid_sources[0x34]	151044	1			T2	47		T4	179		T5	16
valid_sources[0x35]	145916	1			T2	50		T4	210		T5	24
valid_sources[0x36]	156207	1			T2	56		T4	187		T5	17
valid_sources[0x37]	134253	1			T2	61		T4	158		T5	18
valid_sources[0x38]	139652	1			T2	70		T4	178		T5	19
valid_sources[0x39]	171082	1			T2	73		T4	227		T5	37
valid_sources[0x3a]	139734	1			T2	62		T4	182		T5	27
valid_sources[0x3b]	152238	1			T2	63		T4	199		T5	34
valid_sources[0x3c]	141374	1			T2	58		T4	206		T5	30
valid_sources[0x3d]	142553	1			T1	1		T2	52		T4	174
valid_sources[0x3e]	143009	1			T2	61		T4	187		T5	36
valid_sources[0x3f]	143239	1			T2	71		T4	155		T5	14
valid_sources[0x40]	141514	1			T2	56		T4	173		T5	30
valid_sources[0x41]	148042	1			T2	75		T4	196		T5	32
valid_sources[0x42]	137255	1			T2	50		T4	195		T5	15
valid_sources[0x43]	140106	1			T2	49		T4	208		T5	16
valid_sources[0x44]	132555	1			T2	52		T4	185		T5	36
valid_sources[0x45]	153110	1			T2	67		T4	200		T5	23
valid_sources[0x46]	148640	1			T2	64		T4	182		T5	21
valid_sources[0x47]	134227	1			T2	67		T4	207		T5	15
valid_sources[0x48]	154491	1			T2	53		T4	197		T5	23
valid_sources[0x49]	130928	1			T2	47		T4	210		T5	19
valid_sources[0x4a]	151860	1			T2	66		T4	169		T5	16
valid_sources[0x4b]	158681	1			T2	48		T4	222		T5	21
valid_sources[0x4c]	147489	1			T2	56		T4	194		T5	18
valid_sources[0x4d]	149265	1			T2	67		T4	211		T5	27
valid_sources[0x4e]	152429	1			T2	48		T4	174		T5	22
valid_sources[0x4f]	132632	1			T2	71		T4	202		T5	22
valid_sources[0x50]	208692	1			T2	49		T4	199		T5	18
valid_sources[0x51]	144640	1			T2	45		T4	185		T5	24
valid_sources[0x52]	144516	1			T2	75		T3	29		T4	227
valid_sources[0x53]	130431	1			T2	66		T4	188		T5	26
valid_sources[0x54]	149111	1			T2	55		T4	211		T5	18
valid_sources[0x55]	140785	1			T2	65		T4	191		T5	23
valid_sources[0x56]	149424	1			T2	45		T4	202		T5	26
valid_sources[0x57]	183627	1			T2	59		T4	201		T5	13
valid_sources[0x58]	132840	1			T2	56		T4	192		T5	27
valid_sources[0x59]	144893	1			T2	60		T4	207		T5	24
valid_sources[0x5a]	138750	1			T2	63		T4	183		T5	24
valid_sources[0x5b]	144019	1			T2	72		T4	196		T5	22
valid_sources[0x5c]	130834	1			T2	55		T4	174		T5	24
valid_sources[0x5d]	138788	1			T2	54		T4	161		T5	21
valid_sources[0x5e]	151836	1			T2	69		T4	194		T5	24
valid_sources[0x5f]	134725	1			T2	60		T4	206		T5	22
valid_sources[0x60]	149238	1			T2	58		T4	175		T5	19
valid_sources[0x61]	145275	1			T2	50		T4	197		T5	19
valid_sources[0x62]	148989	1			T2	55		T4	204		T5	20
valid_sources[0x63]	139317	1			T2	64		T4	194		T5	17
valid_sources[0x64]	142072	1			T2	79		T4	189		T5	19
valid_sources[0x65]	140332	1			T2	54		T4	184		T5	11
valid_sources[0x66]	134401	1			T2	65		T4	192		T5	24
valid_sources[0x67]	144065	1			T2	60		T4	204		T5	32
valid_sources[0x68]	137739	1			T2	69		T4	202		T5	23
valid_sources[0x69]	150523	1			T2	60		T4	239		T5	16
valid_sources[0x6a]	148213	1			T2	71		T4	172		T5	29
valid_sources[0x6b]	145708	1			T2	57		T4	187		T5	29
valid_sources[0x6c]	143881	1			T2	74		T4	185		T5	19
valid_sources[0x6d]	136951	1			T2	64		T4	215		T5	19
valid_sources[0x6e]	143277	1			T2	60		T4	170		T5	22
valid_sources[0x6f]	141876	1			T2	55		T4	178		T5	24
valid_sources[0x70]	147491	1			T2	73		T4	188		T5	28
valid_sources[0x71]	148465	1			T2	61		T4	171		T5	23
valid_sources[0x72]	147038	1			T2	58		T4	184		T5	17
valid_sources[0x73]	138726	1			T2	57		T4	173		T5	24
valid_sources[0x74]	143122	1			T2	61		T4	180		T5	26
valid_sources[0x75]	140194	1			T2	51		T4	149		T5	23
valid_sources[0x76]	149106	1			T2	48		T4	196		T5	25
valid_sources[0x77]	140931	1			T2	40		T4	167		T5	27
valid_sources[0x78]	136693	1			T2	36		T4	196		T5	15
valid_sources[0x79]	145260	1			T2	56		T4	201		T5	24
valid_sources[0x7a]	151145	1			T2	54		T4	173		T5	21
valid_sources[0x7b]	156387	1			T2	68		T4	170		T5	34
valid_sources[0x7c]	136515	1			T2	68		T4	159		T5	24
valid_sources[0x7d]	160035	1			T2	65		T4	197		T5	35
valid_sources[0x7e]	130709	1			T2	77		T4	194		T5	20
valid_sources[0x7f]	150180	1			T2	47		T4	185		T5	26
valid_sources[0x80]	164534	1			T2	76		T4	172		T5	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7877568

1

T2

3882

T3

9

T4

288

values[0x0]

all_enables

biggest_size

208979

1

T1

12

T2

46

T3

2

values[0x1]

all_enables

biggest_size

144242

1

T1

10

T2

30

T3

1