SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
82.35 | 61.76 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.rx_fifo_level_cg | 41.18 | 1 | 100 | 1 | 64 | 64 |
i2c_env_pkg.fmt_fifo_level_cg | 82.35 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
41.18 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 9 | 3 | 6 | 66.67 |
Crosses | 8 | 7 | 1 | 12.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_fifolvl | 5 | 3 | 2 | 40.00 | 100 | 1 | 1 | 0 | |
cp_irq | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
cp_fifo_threshold_cross | 8 | 7 | 1 | 12.50 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
82.35 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 9 | 0 | 9 | 100.00 |
Crosses | 8 | 3 | 5 | 62.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_fifolvl | 5 | 0 | 5 | 100.00 | 100 | 1 | 1 | 0 | |
cp_irq | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
cp_fifo_threshold_cross | 8 | 3 | 5 | 62.50 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 5 | 3 | 2 | 40.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
lvl[4] | 0 | 1 | 1 | |
lvl[8] | 0 | 1 | 1 | |
lvl[16] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others | 3596 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
lvl[1] | 1 | 1 | T29 | 1 | - | - | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 3572 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
auto[1] | 25 | 1 | T171 | 1 | T239 | 1 | T240 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 997 | 1 | T37 | 10 | T74 | 2 | T52 | 2 | ||||
auto[1] | 2600 | 1 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 8 | 7 | 1 | 12.50 | 7 |
Automatically Generated Cross Bins | 8 | 7 | 1 | 12.50 | 7 |
User Defined Cross Bins | 0 | 0 | 0 |
cp_fifolvl | cp_irq | COUNT | AT LEAST | NUMBER | STATUS |
[lvl[4] , lvl[8] , lvl[16]] | * | -- | -- | 6 |
cp_fifolvl | cp_irq | COUNT | AT LEAST | NUMBER | STATUS |
[lvl[1]] | [auto[1]] | 0 | 1 | 1 |
cp_fifolvl | cp_irq | COUNT | AT LEAST | STATUS | TEST | COUNT | |
lvl[1] | auto[0] | 1 | 1 | T29 | 1 |
NAME | COUNT | STATUS |
reserved_values | 0 | Excluded |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 5 | 0 | 5 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others | 3260 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
lvl[1] | 215 | 1 | T83 | 1 | T38 | 4 | T39 | 2 | ||||
lvl[4] | 66 | 1 | T242 | 2 | T243 | 4 | T244 | 2 | ||||
lvl[8] | 50 | 1 | T37 | 2 | T38 | 4 | T242 | 2 | ||||
lvl[16] | 6 | 1 | T245 | 2 | T246 | 2 | T247 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2959 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
auto[1] | 638 | 1 | T74 | 2 | T52 | 2 | T96 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 636 | 1 | T37 | 5 | T74 | 2 | T52 | 2 | ||||
auto[1] | 2961 | 1 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 8 | 3 | 5 | 62.50 | 3 |
Automatically Generated Cross Bins | 8 | 3 | 5 | 62.50 | 3 |
User Defined Cross Bins | 0 | 0 | 0 |
cp_fifolvl | cp_irq | COUNT | AT LEAST | NUMBER | STATUS |
[lvl[4] , lvl[8] , lvl[16]] | [auto[1]] | -- | -- | 3 |
cp_fifolvl | cp_irq | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
lvl[1] | auto[0] | 206 | 1 | T38 | 4 | T39 | 2 | T242 | 2 | ||||
lvl[1] | auto[1] | 9 | 1 | T83 | 1 | T248 | 2 | T113 | 1 | ||||
lvl[4] | auto[0] | 66 | 1 | T242 | 2 | T243 | 4 | T244 | 2 | ||||
lvl[8] | auto[0] | 50 | 1 | T37 | 2 | T38 | 4 | T242 | 2 | ||||
lvl[16] | auto[0] | 6 | 1 | T245 | 2 | T246 | 2 | T247 | 2 |
NAME | COUNT | STATUS |
reserved_values | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |