Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	394574158	0	0	0
ctrl_rd_A	394574158	2646	0	0
host_fifo_config_rd_A	394574158	5016	0	0
host_nack_handler_timeout_rd_A	394574158	1408	0	0
host_timeout_ctrl_rd_A	394574158	1184	0	0
intr_enable_rd_A	394574158	4549	0	0
ovrd_rd_A	394574158	2479	0	0
target_fifo_config_rd_A	394574158	1499	0	0
target_id_rd_A	394574158	1836	0	0
target_timeout_ctrl_rd_A	394574158	1269	0	0
timeout_ctrl_rd_A	394574158	1802	0	0
timing0_rd_A	394574158	1410	0	0
timing1_rd_A	394574158	1475	0	0
timing2_rd_A	394574158	1411	0	0
timing3_rd_A	394574158	1439	0	0
timing4_rd_A	394574158	1391	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	2646	0	0
T99	13564	292	0	0
T100	6538	6	0	0
T101	2990	13	0	0
T102	3660	9	0	0
T103	2257	43	0	0
T104	3356	70	0	0
T105	12661	242	0	0
T106	2741	28	0	0
T107	5518	11	0	0
T108	14930	413	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	5016	0	0
T24	17563	0	0	0
T25	20222	0	0	0
T40	0	198	0	0
T109	404599	180	0	0
T110	0	85	0	0
T111	0	140	0	0
T112	0	124	0	0
T113	0	325	0	0
T114	0	149	0	0
T115	0	111	0	0
T116	0	97	0	0
T117	0	105	0	0
T118	108420	0	0	0
T119	8584	0	0	0
T120	47736	0	0	0
T121	314187	0	0	0
T122	634070	0	0	0
T123	359642	0	0	0
T124	10255	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1408	0	0
T99	13564	70	0	0
T100	6538	18	0	0
T101	2990	17	0	0
T102	3660	9	0	0
T103	2257	17	0	0
T104	3356	25	0	0
T105	12661	144	0	0
T106	2741	6	0	0
T107	5518	69	0	0
T108	14930	115	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1184	0	0
T99	13564	82	0	0
T100	6538	14	0	0
T101	2990	17	0	0
T102	3660	5	0	0
T103	2257	6	0	0
T104	3356	16	0	0
T105	12661	73	0	0
T107	5518	38	0	0
T108	14930	80	0	0
T125	13503	57	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	4549	0	0
T30	0	40	0	0
T33	0	5	0	0
T40	100218	5	0	0
T99	0	623	0	0
T100	0	33	0	0
T101	0	110	0	0
T102	0	27	0	0
T103	0	70	0	0
T113	0	74	0	0
T126	0	4	0	0
T127	20094	0	0	0
T128	135704	0	0	0
T129	260563	0	0	0
T130	18021	0	0	0
T131	100519	0	0	0
T132	136417	0	0	0
T133	45002	0	0	0
T134	1334	0	0	0
T135	27519	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	2479	0	0
T35	156197	0	0	0
T50	180557	0	0	0
T53	96095	0	0	0
T61	926546	0	0	0
T70	21619	0	0	0
T71	121905	0	0	0
T72	143070	0	0	0
T73	7123	0	0	0
T80	1639	87	0	0
T81	0	84	0	0
T95	0	43	0	0
T136	0	61	0	0
T137	0	29	0	0
T138	0	27	0	0
T139	0	49	0	0
T140	0	36	0	0
T141	0	60	0	0
T142	0	51	0	0
T143	45099	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1499	0	0
T99	13564	168	0	0
T100	6538	26	0	0
T101	2990	6	0	0
T102	3660	24	0	0
T103	2257	19	0	0
T104	3356	16	0	0
T105	12661	109	0	0
T106	2741	4	0	0
T107	5518	59	0	0
T108	14930	103	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1836	0	0
T99	13564	199	0	0
T100	6538	4	0	0
T101	2990	38	0	0
T102	3660	7	0	0
T103	2257	11	0	0
T104	3356	40	0	0
T105	12661	217	0	0
T106	2741	9	0	0
T107	5518	7	0	0
T108	14930	215	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1269	0	0
T99	13564	96	0	0
T100	6538	8	0	0
T101	2990	35	0	0
T102	3660	10	0	0
T103	2257	6	0	0
T104	3356	12	0	0
T105	12661	85	0	0
T106	2741	5	0	0
T107	5518	50	0	0
T108	14930	139	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1802	0	0
T99	13564	160	0	0
T100	6538	24	0	0
T101	2990	12	0	0
T102	3660	16	0	0
T103	2257	8	0	0
T104	3356	38	0	0
T105	12661	135	0	0
T106	2741	13	0	0
T107	5518	84	0	0
T108	14930	147	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1410	0	0
T99	13564	168	0	0
T100	6538	9	0	0
T101	2990	24	0	0
T102	3660	2	0	0
T103	2257	30	0	0
T104	3356	18	0	0
T105	12661	111	0	0
T106	2741	11	0	0
T107	5518	26	0	0
T108	14930	131	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1475	0	0
T99	13564	121	0	0
T100	6538	16	0	0
T101	2990	18	0	0
T102	3660	36	0	0
T103	2257	6	0	0
T104	3356	23	0	0
T105	12661	116	0	0
T106	2741	5	0	0
T107	5518	27	0	0
T108	14930	79	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1411	0	0
T99	13564	96	0	0
T100	6538	11	0	0
T101	2990	10	0	0
T102	3660	11	0	0
T103	2257	17	0	0
T104	3356	11	0	0
T105	12661	91	0	0
T106	2741	9	0	0
T107	5518	20	0	0
T108	14930	127	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1439	0	0
T99	13564	125	0	0
T101	2990	9	0	0
T102	3660	14	0	0
T103	2257	10	0	0
T104	3356	30	0	0
T105	12661	116	0	0
T106	2741	6	0	0
T107	5518	17	0	0
T108	14930	150	0	0
T125	13503	78	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394574158	1391	0	0
T99	13564	101	0	0
T100	6538	22	0	0
T101	2990	22	0	0
T102	3660	4	0	0
T103	2257	11	0	0
T104	3356	18	0	0
T105	12661	126	0	0
T106	2741	4	0	0
T107	5518	34	0	0
T108	14930	139	0	0