Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 30397526 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 8307322 1 T1 717 T2 1542 T3 7376



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 37841964 1 T1 2849 T2 4510 T3 47500
values[0x0] 430621 1 T1 15 T2 964 T3 1442
values[0x1] 432263 1 T1 12 T2 908 T3 1483



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 21258540 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 17446308 1 T1 1310 T2 2995 T3 20656



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 142644 1 T1 16 T2 23 T3 148
valid_sources[0x01] 154785 1 T1 6 T2 20 T3 111
valid_sources[0x02] 166749 1 T1 8 T2 35 T3 162
valid_sources[0x03] 155552 1 T1 11 T2 32 T3 127
valid_sources[0x04] 129649 1 T1 19 T2 23 T3 208
valid_sources[0x05] 183732 1 T1 3 T2 21 T3 205
valid_sources[0x06] 140689 1 T1 9 T2 21 T3 203
valid_sources[0x07] 151979 1 T1 13 T2 26 T3 286
valid_sources[0x08] 175442 1 T1 16 T2 17 T3 236
valid_sources[0x09] 156008 1 T1 18 T2 26 T3 220
valid_sources[0x0a] 155735 1 T1 8 T2 20 T3 210
valid_sources[0x0b] 165533 1 T1 9 T2 29 T3 130
valid_sources[0x0c] 159039 1 T1 14 T2 20 T3 224
valid_sources[0x0d] 153062 1 T1 19 T2 27 T3 130
valid_sources[0x0e] 160790 1 T1 6 T2 17 T3 209
valid_sources[0x0f] 155242 1 T1 16 T2 17 T3 168
valid_sources[0x10] 135548 1 T1 6 T2 22 T3 141
valid_sources[0x11] 151319 1 T1 5 T2 22 T3 171
valid_sources[0x12] 137187 1 T1 5 T2 24 T3 260
valid_sources[0x13] 146073 1 T1 14 T2 35 T3 202
valid_sources[0x14] 146886 1 T1 14 T2 29 T3 150
valid_sources[0x15] 168484 1 T1 11 T2 17 T3 200
valid_sources[0x16] 154424 1 T1 23 T2 13 T3 263
valid_sources[0x17] 156136 1 T1 26 T2 25 T3 236
valid_sources[0x18] 143531 1 T1 13 T2 31 T3 300
valid_sources[0x19] 161627 1 T1 12 T2 28 T3 210
valid_sources[0x1a] 142225 1 T1 6 T2 22 T3 126
valid_sources[0x1b] 148405 1 T1 13 T2 30 T3 295
valid_sources[0x1c] 141067 1 T1 20 T2 18 T3 196
valid_sources[0x1d] 139289 1 T1 8 T2 17 T3 228
valid_sources[0x1e] 144206 1 T1 12 T2 22 T3 128
valid_sources[0x1f] 141826 1 T1 5 T2 26 T3 92
valid_sources[0x20] 149208 1 T1 12 T2 15 T3 148
valid_sources[0x21] 135665 1 T1 16 T2 17 T3 192
valid_sources[0x22] 151634 1 T1 8 T2 27 T3 157
valid_sources[0x23] 142429 1 T1 14 T2 28 T3 168
valid_sources[0x24] 138603 1 T1 12 T2 31 T3 197
valid_sources[0x25] 148534 1 T1 10 T2 24 T3 196
valid_sources[0x26] 149976 1 T1 8 T2 25 T3 189
valid_sources[0x27] 132989 1 T1 13 T2 24 T3 117
valid_sources[0x28] 151710 1 T1 20 T2 19 T3 163
valid_sources[0x29] 135205 1 T1 11 T2 28 T3 177
valid_sources[0x2a] 134749 1 T1 5 T2 33 T3 185
valid_sources[0x2b] 143390 1 T1 7 T2 26 T3 108
valid_sources[0x2c] 143974 1 T1 8 T2 12 T3 237
valid_sources[0x2d] 142680 1 T1 21 T2 25 T3 217
valid_sources[0x2e] 168932 1 T1 5 T2 27 T3 163
valid_sources[0x2f] 139042 1 T1 10 T2 30 T3 215
valid_sources[0x30] 142562 1 T1 2 T2 29 T3 237
valid_sources[0x31] 142550 1 T1 24 T2 30 T3 261
valid_sources[0x32] 153612 1 T1 17 T2 19 T3 240
valid_sources[0x33] 140027 1 T1 25 T2 34 T3 128
valid_sources[0x34] 145246 1 T1 9 T2 24 T3 180
valid_sources[0x35] 154848 1 T1 12 T2 21 T3 205
valid_sources[0x36] 143753 1 T1 5 T2 30 T3 238
valid_sources[0x37] 153010 1 T1 9 T2 29 T3 184
valid_sources[0x38] 141467 1 T1 9 T2 22 T3 180
valid_sources[0x39] 150191 1 T1 10 T2 31 T3 233
valid_sources[0x3a] 149586 1 T1 4 T2 25 T3 305
valid_sources[0x3b] 141333 1 T1 12 T2 31 T3 187
valid_sources[0x3c] 145732 1 T1 6 T2 21 T3 155
valid_sources[0x3d] 153944 1 T1 7 T2 26 T3 130
valid_sources[0x3e] 151491 1 T1 32 T2 23 T3 274
valid_sources[0x3f] 168112 1 T1 7 T2 24 T3 183
valid_sources[0x40] 149533 1 T1 7 T2 20 T3 299
valid_sources[0x41] 162702 1 T1 5 T2 20 T3 228
valid_sources[0x42] 158440 1 T1 11 T2 28 T3 244
valid_sources[0x43] 160263 1 T1 15 T2 18 T3 262
valid_sources[0x44] 145496 1 T1 7 T2 27 T3 161
valid_sources[0x45] 148128 1 T1 18 T2 27 T3 182
valid_sources[0x46] 153579 1 T1 14 T2 25 T3 136
valid_sources[0x47] 140136 1 T1 14 T2 19 T3 142
valid_sources[0x48] 156709 1 T1 6 T2 23 T3 233
valid_sources[0x49] 141715 1 T1 22 T2 25 T3 208
valid_sources[0x4a] 242232 1 T1 13 T2 24 T3 163
valid_sources[0x4b] 174700 1 T1 10 T2 16 T3 201
valid_sources[0x4c] 160022 1 T1 4 T2 20 T3 130
valid_sources[0x4d] 133680 1 T1 8 T2 23 T3 125
valid_sources[0x4e] 142552 1 T1 25 T2 17 T3 262
valid_sources[0x4f] 160810 1 T1 11 T2 30 T3 134
valid_sources[0x50] 136308 1 T1 8 T2 22 T3 246
valid_sources[0x51] 192279 1 T1 14 T2 33 T3 144
valid_sources[0x52] 155681 1 T1 10 T2 24 T3 176
valid_sources[0x53] 150195 1 T1 8 T2 24 T3 178
valid_sources[0x54] 158690 1 T1 18 T2 24 T3 136
valid_sources[0x55] 144315 1 T1 14 T2 33 T3 190
valid_sources[0x56] 149252 1 T1 11 T2 34 T3 159
valid_sources[0x57] 151610 1 T1 12 T2 25 T3 124
valid_sources[0x58] 154722 1 T1 8 T2 34 T3 185
valid_sources[0x59] 154693 1 T1 5 T2 20 T3 265
valid_sources[0x5a] 158421 1 T1 14 T2 20 T3 187
valid_sources[0x5b] 148916 1 T1 10 T2 24 T3 220
valid_sources[0x5c] 150877 1 T1 15 T2 21 T3 236
valid_sources[0x5d] 146758 1 T1 10 T2 25 T3 268
valid_sources[0x5e] 166991 1 T1 18 T2 21 T3 191
valid_sources[0x5f] 164893 1 T1 10 T2 26 T3 276
valid_sources[0x60] 145965 1 T1 3 T2 22 T3 174
valid_sources[0x61] 148686 1 T1 9 T2 31 T3 126
valid_sources[0x62] 159100 1 T1 12 T2 29 T3 195
valid_sources[0x63] 156611 1 T1 13 T2 28 T3 247
valid_sources[0x64] 168173 1 T1 12 T2 12 T3 297
valid_sources[0x65] 146476 1 T1 22 T2 22 T3 240
valid_sources[0x66] 165557 1 T1 10 T2 29 T3 238
valid_sources[0x67] 156673 1 T1 14 T2 19 T3 220
valid_sources[0x68] 139834 1 T1 13 T2 31 T3 250
valid_sources[0x69] 137238 1 T1 2 T2 20 T3 174
valid_sources[0x6a] 155852 1 T1 24 T2 26 T3 113
valid_sources[0x6b] 160610 1 T1 7 T2 22 T3 217
valid_sources[0x6c] 133430 1 T1 15 T2 29 T3 166
valid_sources[0x6d] 167786 1 T1 9 T2 29 T3 181
valid_sources[0x6e] 141403 1 T1 7 T2 25 T3 174
valid_sources[0x6f] 147006 1 T1 10 T2 27 T3 241
valid_sources[0x70] 131573 1 T1 10 T2 23 T3 301
valid_sources[0x71] 145914 1 T1 12 T2 26 T3 100
valid_sources[0x72] 138844 1 T1 15 T2 29 T3 236
valid_sources[0x73] 153628 1 T1 8 T2 23 T3 164
valid_sources[0x74] 153581 1 T1 21 T2 21 T3 180
valid_sources[0x75] 130202 1 T1 7 T2 25 T3 196
valid_sources[0x76] 176315 1 T1 7 T2 27 T3 219
valid_sources[0x77] 155275 1 T1 10 T2 24 T3 182
valid_sources[0x78] 149944 1 T1 8 T2 23 T3 213
valid_sources[0x79] 155619 1 T1 8 T2 28 T3 150
valid_sources[0x7a] 143319 1 T1 16 T2 19 T3 189
valid_sources[0x7b] 156687 1 T1 11 T2 28 T3 160
valid_sources[0x7c] 161424 1 T1 10 T2 18 T3 268
valid_sources[0x7d] 147354 1 T1 7 T2 26 T3 188
valid_sources[0x7e] 278120 1 T1 19 T2 34 T3 169
valid_sources[0x7f] 151912 1 T1 13 T2 30 T3 206
valid_sources[0x80] 163284 1 T1 8 T2 23 T3 177



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7926181 1 T1 702 T2 818 T3 6250
values[0x0] all_enables biggest_size 226237 1 T1 9 T2 428 T3 734
values[0x1] all_enables biggest_size 154904 1 T1 6 T2 296 T3 392

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%