Unified Coverage Report :: Group :: i2c_env_pkg::i2c_acq_fifo_cg

Group : i2c_env_pkg::i2c_acq_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.acq_fifo_cg	95.83	1	100	1	64	64

---

Group Instance : i2c_env_pkg.acq_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.acq_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	13	1	12	92.31

Variables for Group Instance i2c_env_pkg.acq_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_abyte	5	0	5	100.00	100	1	1	0
cp_action	4	0	4	100.00	100	1	1	0
cp_request_type	2	0	2	100.00	100	1	1	0
cp_target_read_ack_nack	0	0	0				1	0

Crosses for Group Instance i2c_env_pkg.acq_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_abyte_X_cp_action	13	1	12	92.31	100	1	1	0

Summary for Variable cp_abyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_abyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	1073	1			T2	4		T4	1		T5	2
high	59415	1			T2	254		T4	41		T5	58
med	112416	1			T2	562		T4	110		T5	99
sml	111193	1			T2	620		T4	90		T5	109
all_zero	1250	1			T2	1		T10	1		T45	7

---

Summary for Variable cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_action

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
rstart	32905	1			T2	227		T5	32		T6	7
start	12609	1			T2	71		T4	1		T5	2
stop	12649	1			T2	71		T4	1		T5	1
none	227184	1			T2	1072		T4	240		T5	233

---

Summary for Variable cp_request_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_request_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

write

6460

1

T2

38

T4

1

T5

2

read

6149

1

T2

33

T6

6

T7

1

---

Summary for Variable cp_target_read_ack_nack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	0	0	0

User Defined Bins for cp_target_read_ack_nack

Excluded/Illegal bins

NAME	COUNT	STATUS
read_req_nack_before_rstart	0	Excluded
read_req_ack_before_stop	0	Excluded
read_req_nack_before_stop	0	Excluded
read_req_ack_before_rstart	0	Excluded

---

Summary for Cross cp_abyte_X_cp_action

Samples crossed: cp_abyte cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	13	1	12	92.31	1
Automatically Generated Cross Bins	10	1	9	90.00	1
User Defined Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for cp_abyte_X_cp_action

Uncovered bins

cp_abyte	cp_action	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[stop]	0	1	1

Covered bins

cp_abyte	cp_action	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	rstart	127	1			T188	7		T267	2		T268	35
high	rstart	6534	1			T45	28		T54	42		T114	9
high	stop	2706	1			T2	16		T6	2		T7	1
med	rstart	13480	1			T2	80		T6	2		T8	17
med	stop	4969	1			T2	27		T4	1		T5	1
sml	rstart	12638	1			T2	147		T5	32		T6	5
sml	stop	4873	1			T2	27		T6	5		T8	1
all_zero	rstart	126	1			T269	12		T270	14		T76	12
all_zero	stop	101	1			T2	1		T45	1		T54	1

User Defined Cross Bins for cp_abyte_X_cp_action

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
write_address_byte	12609	1			T2	71		T4	1		T5	2
read_address_byte	12609	1			T2	71		T4	1		T5	2
data_byte	227184	1			T2	1072		T4	240		T5	233