Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	387150434	0	0	0
ctrl_rd_A	387150434	2239	0	0
host_fifo_config_rd_A	387150434	5466	0	0
host_nack_handler_timeout_rd_A	387150434	1570	0	0
host_timeout_ctrl_rd_A	387150434	1348	0	0
intr_enable_rd_A	387150434	3910	0	0
ovrd_rd_A	387150434	2419	0	0
target_fifo_config_rd_A	387150434	1523	0	0
target_id_rd_A	387150434	2014	0	0
target_timeout_ctrl_rd_A	387150434	1689	0	0
timeout_ctrl_rd_A	387150434	1751	0	0
timing0_rd_A	387150434	1460	0	0
timing1_rd_A	387150434	1479	0	0
timing2_rd_A	387150434	1445	0	0
timing3_rd_A	387150434	1575	0	0
timing4_rd_A	387150434	1467	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	2239	0	0
T94	11482	42	0	0
T95	8493	156	0	0
T96	4651	19	0	0
T97	1745	16	0	0
T98	26433	199	0	0
T99	1823	28	0	0
T100	12384	45	0	0
T101	2787	56	0	0
T102	15164	230	0	0
T103	6481	127	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	5466	0	0
T17	644117	0	0	0
T23	34311	0	0	0
T33	483816	208	0	0
T44	36167	0	0	0
T52	41067	0	0	0
T64	102680	0	0	0
T72	14137	0	0	0
T74	0	157	0	0
T104	0	158	0	0
T105	0	90	0	0
T106	0	140	0	0
T107	0	207	0	0
T108	0	115	0	0
T109	0	207	0	0
T110	0	105	0	0
T111	0	164	0	0
T112	138028	0	0	0
T113	530517	0	0	0
T114	79347	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	1570	0	0
T94	11482	35	0	0
T95	8493	60	0	0
T96	4651	27	0	0
T97	1745	4	0	0
T98	26433	240	0	0
T99	1823	9	0	0
T100	12384	13	0	0
T101	2787	20	0	0
T102	15164	95	0	0
T115	3298	43	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	1348	0	0
T94	11482	33	0	0
T95	8493	31	0	0
T96	4651	46	0	0
T97	1745	5	0	0
T98	26433	206	0	0
T99	1823	6	0	0
T100	12384	56	0	0
T101	2787	24	0	0
T102	15164	77	0	0
T115	3298	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	3910	0	0
T71	13258	0	0	0
T94	0	7	0	0
T95	0	378	0	0
T96	0	16	0	0
T105	0	8	0	0
T115	0	41	0	0
T116	338530	30	0	0
T117	0	5	0	0
T118	0	6	0	0
T119	0	34	0	0
T120	0	98	0	0
T121	137804	0	0	0
T122	254178	0	0	0
T123	31247	0	0	0
T124	11783	0	0	0
T125	44364	0	0	0
T126	43580	0	0	0
T127	70438	0	0	0
T128	17639	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	2419	0	0
T11	9469	0	0	0
T129	2568	39	0	0
T130	0	67	0	0
T131	0	39	0	0
T132	0	35	0	0
T133	0	58	0	0
T134	0	9	0	0
T135	0	35	0	0
T136	0	54	0	0
T137	0	54	0	0
T138	0	49	0	0
T139	18600	0	0	0
T140	11798	0	0	0
T141	847573	0	0	0
T142	72395	0	0	0
T143	17925	0	0	0
T144	308849	0	0	0
T145	13809	0	0	0
T146	161271	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	1523	0	0
T94	11482	34	0	0
T95	8493	60	0	0
T96	4651	37	0	0
T97	1745	3	0	0
T98	26433	231	0	0
T99	1823	7	0	0
T100	12384	18	0	0
T101	2787	28	0	0
T102	15164	137	0	0
T115	3298	33	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	2014	0	0
T94	11482	22	0	0
T95	8493	112	0	0
T96	4651	80	0	0
T97	1745	26	0	0
T98	26433	262	0	0
T99	1823	2	0	0
T100	12384	33	0	0
T101	2787	27	0	0
T102	15164	202	0	0
T115	3298	38	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	1689	0	0
T94	11482	20	0	0
T95	8493	66	0	0
T96	4651	47	0	0
T97	1745	14	0	0
T98	26433	267	0	0
T99	1823	5	0	0
T100	12384	22	0	0
T101	2787	22	0	0
T102	15164	108	0	0
T115	3298	34	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	1751	0	0
T94	11482	28	0	0
T95	8493	74	0	0
T96	4651	51	0	0
T98	26433	212	0	0
T99	1823	6	0	0
T100	12384	38	0	0
T101	2787	12	0	0
T102	15164	139	0	0
T103	6481	149	0	0
T115	3298	11	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	1460	0	0
T94	11482	17	0	0
T95	8493	43	0	0
T96	4651	21	0	0
T97	1745	7	0	0
T98	26433	216	0	0
T99	1823	8	0	0
T100	12384	30	0	0
T101	2787	26	0	0
T102	15164	109	0	0
T115	3298	6	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	1479	0	0
T94	11482	49	0	0
T95	8493	51	0	0
T96	4651	53	0	0
T97	1745	3	0	0
T98	26433	222	0	0
T99	1823	7	0	0
T100	12384	28	0	0
T101	2787	20	0	0
T102	15164	135	0	0
T115	3298	7	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	1445	0	0
T94	11482	14	0	0
T95	8493	69	0	0
T96	4651	63	0	0
T97	1745	6	0	0
T98	26433	207	0	0
T99	1823	6	0	0
T100	12384	16	0	0
T101	2787	18	0	0
T102	15164	133	0	0
T115	3298	1	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	1575	0	0
T94	11482	22	0	0
T95	8493	50	0	0
T96	4651	27	0	0
T97	1745	2	0	0
T98	26433	238	0	0
T99	1823	8	0	0
T100	12384	29	0	0
T101	2787	13	0	0
T102	15164	93	0	0
T115	3298	38	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387150434	1467	0	0
T94	11482	17	0	0
T95	8493	55	0	0
T96	4651	53	0	0
T97	1745	4	0	0
T98	26433	230	0	0
T99	1823	17	0	0
T100	12384	25	0	0
T101	2787	14	0	0
T102	15164	93	0	0
T115	3298	26	0	0