Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24784217	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6467342

1

T1

1686

T2

6279

T3

329

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	30476785	1			T1	10713		T2	12859		T3	922
values[0x0]	387384	1			T1	272		T2	56		T3	192
values[0x1]	387390	1			T1	235		T2	58		T3	240

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17269036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13982523

1

T1

4589

T2

7649

T3

603

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	129730	1			T1	32		T3	2		T4	42
valid_sources[0x01]	116766	1			T1	40		T3	2		T9	8
valid_sources[0x02]	123151	1			T1	37		T3	6		T4	42
valid_sources[0x03]	115242	1			T1	35		T3	6		T9	8
valid_sources[0x04]	125821	1			T1	44		T3	3		T4	100
valid_sources[0x05]	110888	1			T1	33		T3	8		T9	2
valid_sources[0x06]	113779	1			T1	32		T3	6		T9	1
valid_sources[0x07]	126572	1			T1	56		T3	6		T4	209
valid_sources[0x08]	108729	1			T1	48		T3	5		T9	4
valid_sources[0x09]	136216	1			T1	41		T3	3		T10	172
valid_sources[0x0a]	111374	1			T1	46		T3	6		T4	103
valid_sources[0x0b]	126204	1			T1	39		T3	4		T4	43
valid_sources[0x0c]	114313	1			T1	46		T3	4		T9	1
valid_sources[0x0d]	115209	1			T1	39		T3	5		T4	54
valid_sources[0x0e]	122895	1			T1	39		T3	5		T4	42
valid_sources[0x0f]	107018	1			T1	32		T2	1162		T3	5
valid_sources[0x10]	134709	1			T1	28		T3	3		T7	1
valid_sources[0x11]	130777	1			T1	57		T3	7		T6	2
valid_sources[0x12]	131744	1			T1	45		T2	1		T3	8
valid_sources[0x13]	114584	1			T1	43		T3	13		T4	95
valid_sources[0x14]	127180	1			T1	50		T3	8		T4	39
valid_sources[0x15]	125380	1			T1	55		T3	5		T4	445
valid_sources[0x16]	132630	1			T1	55		T3	8		T9	3
valid_sources[0x17]	117171	1			T1	51		T2	1		T3	5
valid_sources[0x18]	134659	1			T1	38		T3	1		T4	113
valid_sources[0x19]	113640	1			T1	28		T2	1		T3	4
valid_sources[0x1a]	119174	1			T1	46		T3	6		T4	1217
valid_sources[0x1b]	124871	1			T1	55		T3	5		T5	2
valid_sources[0x1c]	118069	1			T1	44		T3	6		T4	39
valid_sources[0x1d]	120525	1			T1	46		T2	1		T3	3
valid_sources[0x1e]	115017	1			T1	39		T3	6		T4	374
valid_sources[0x1f]	126359	1			T1	44		T3	4		T4	156
valid_sources[0x20]	119601	1			T1	46		T3	5		T4	141
valid_sources[0x21]	118813	1			T1	44		T3	4		T4	38
valid_sources[0x22]	122799	1			T1	37		T3	6		T4	90
valid_sources[0x23]	119556	1			T1	59		T3	3		T4	45
valid_sources[0x24]	135180	1			T1	43		T3	7		T4	48
valid_sources[0x25]	108379	1			T1	50		T3	9		T7	2
valid_sources[0x26]	119489	1			T1	46		T2	1		T3	7
valid_sources[0x27]	117972	1			T1	39		T3	3		T5	3
valid_sources[0x28]	117211	1			T1	32		T3	4		T4	374
valid_sources[0x29]	116103	1			T1	30		T3	9		T9	1
valid_sources[0x2a]	145857	1			T1	44		T3	5		T4	51
valid_sources[0x2b]	121138	1			T1	47		T3	8		T4	574
valid_sources[0x2c]	119707	1			T1	44		T2	1		T3	4
valid_sources[0x2d]	128383	1			T1	59		T3	4		T7	1
valid_sources[0x2e]	131244	1			T1	46		T3	7		T4	307
valid_sources[0x2f]	141785	1			T1	43		T3	4		T4	92
valid_sources[0x30]	116663	1			T1	48		T3	2		T4	145
valid_sources[0x31]	118726	1			T1	57		T3	9		T9	9
valid_sources[0x32]	123818	1			T1	44		T3	4		T9	4
valid_sources[0x33]	116633	1			T1	48		T3	8		T4	45
valid_sources[0x34]	121208	1			T1	44		T3	6		T9	6
valid_sources[0x35]	122370	1			T1	39		T3	4		T4	53
valid_sources[0x36]	117203	1			T1	38		T3	4		T9	4
valid_sources[0x37]	114052	1			T1	42		T2	1		T3	4
valid_sources[0x38]	109241	1			T1	40		T3	3		T9	1
valid_sources[0x39]	121608	1			T1	40		T3	6		T7	2
valid_sources[0x3a]	112031	1			T1	39		T2	2333		T3	7
valid_sources[0x3b]	128139	1			T1	51		T3	4		T7	2
valid_sources[0x3c]	117732	1			T1	49		T3	3		T4	39
valid_sources[0x3d]	111665	1			T1	41		T3	7		T7	1
valid_sources[0x3e]	122597	1			T1	58		T3	7		T9	1
valid_sources[0x3f]	124899	1			T1	46		T3	5		T9	8
valid_sources[0x40]	116824	1			T1	49		T2	1		T3	6
valid_sources[0x41]	114445	1			T1	45		T3	4		T9	2
valid_sources[0x42]	126629	1			T1	47		T2	1		T3	3
valid_sources[0x43]	123662	1			T1	43		T3	5		T7	6
valid_sources[0x44]	126601	1			T1	35		T3	6		T4	1312
valid_sources[0x45]	125830	1			T1	31		T2	1161		T3	5
valid_sources[0x46]	114103	1			T1	36		T3	4		T4	87
valid_sources[0x47]	123121	1			T1	39		T3	7		T4	52
valid_sources[0x48]	118819	1			T1	50		T3	5		T9	10
valid_sources[0x49]	115361	1			T1	48		T3	4		T9	1
valid_sources[0x4a]	124879	1			T1	45		T3	8		T9	5
valid_sources[0x4b]	128602	1			T1	51		T3	6		T9	1
valid_sources[0x4c]	121902	1			T1	36		T3	6		T9	3
valid_sources[0x4d]	128523	1			T1	36		T3	5		T4	39
valid_sources[0x4e]	124959	1			T1	41		T3	4		T4	81
valid_sources[0x4f]	136357	1			T1	53		T3	6		T4	57
valid_sources[0x50]	119706	1			T1	40		T3	1		T4	105
valid_sources[0x51]	146406	1			T1	44		T3	5		T4	308
valid_sources[0x52]	128023	1			T1	37		T3	5		T4	52
valid_sources[0x53]	122133	1			T1	44		T3	7		T10	96
valid_sources[0x54]	115063	1			T1	50		T3	2		T4	43
valid_sources[0x55]	124706	1			T1	49		T2	1		T3	6
valid_sources[0x56]	119021	1			T1	37		T3	2		T10	175
valid_sources[0x57]	113356	1			T1	37		T3	7		T4	98
valid_sources[0x58]	108676	1			T1	44		T3	4		T4	137
valid_sources[0x59]	157623	1			T1	50		T2	2650		T3	7
valid_sources[0x5a]	117790	1			T1	50		T3	8		T4	1776
valid_sources[0x5b]	108704	1			T1	43		T3	3		T9	2
valid_sources[0x5c]	120662	1			T1	47		T3	3		T4	65
valid_sources[0x5d]	122666	1			T1	36		T3	7		T9	8
valid_sources[0x5e]	112203	1			T1	49		T3	5		T4	51
valid_sources[0x5f]	134936	1			T1	49		T3	4		T4	151
valid_sources[0x60]	114873	1			T1	48		T3	4		T9	7
valid_sources[0x61]	112659	1			T1	27		T3	4		T10	136
valid_sources[0x62]	128340	1			T1	36		T3	10		T9	10
valid_sources[0x63]	119986	1			T1	36		T2	2695		T3	5
valid_sources[0x64]	132186	1			T1	51		T3	4		T4	211
valid_sources[0x65]	124683	1			T1	44		T3	5		T4	491
valid_sources[0x66]	116138	1			T1	39		T2	1		T3	13
valid_sources[0x67]	134839	1			T1	46		T3	4		T9	1
valid_sources[0x68]	122137	1			T1	49		T3	3		T10	122
valid_sources[0x69]	127037	1			T1	46		T3	8		T9	2
valid_sources[0x6a]	121463	1			T1	53		T3	5		T4	1223
valid_sources[0x6b]	114149	1			T1	46		T3	3		T4	42
valid_sources[0x6c]	111297	1			T1	38		T3	4		T4	192
valid_sources[0x6d]	124693	1			T1	47		T3	4		T9	7
valid_sources[0x6e]	121230	1			T1	43		T3	4		T4	101
valid_sources[0x6f]	122400	1			T1	54		T3	5		T4	50
valid_sources[0x70]	115177	1			T1	37		T3	8		T4	93
valid_sources[0x71]	124428	1			T1	36		T3	4		T4	94
valid_sources[0x72]	119850	1			T1	30		T3	3		T7	1
valid_sources[0x73]	119690	1			T1	40		T3	6		T4	1697
valid_sources[0x74]	113351	1			T1	52		T3	4		T4	93
valid_sources[0x75]	116909	1			T1	51		T3	6		T4	80
valid_sources[0x76]	114735	1			T1	49		T3	7		T9	5
valid_sources[0x77]	113918	1			T1	36		T3	5		T4	2988
valid_sources[0x78]	114283	1			T1	30		T3	6		T10	103
valid_sources[0x79]	125627	1			T1	56		T3	3		T4	57
valid_sources[0x7a]	113554	1			T1	39		T3	7		T9	3
valid_sources[0x7b]	129947	1			T1	41		T3	7		T5	2
valid_sources[0x7c]	145550	1			T1	46		T3	8		T4	111
valid_sources[0x7d]	123916	1			T1	54		T3	8		T4	300
valid_sources[0x7e]	123805	1			T1	32		T2	1573		T3	2
valid_sources[0x7f]	125301	1			T1	34		T3	2		T4	55
valid_sources[0x80]	112829	1			T1	44		T3	5		T9	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6119972

1

T1

1345

T2

6188

T3

201

values[0x0]

all_enables

biggest_size

205309

1

T1

186

T2

47

T3

77

values[0x1]

all_enables

biggest_size

142061

1

T1

155

T2

44

T3

51