Unified Coverage Report :: Group :: i2c_env_pkg::i2c_acq_fifo_cg

Group : i2c_env_pkg::i2c_acq_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.acq_fifo_cg	95.83	1	100	1	64	64

---

Group Instance : i2c_env_pkg.acq_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.acq_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	13	1	12	92.31

Variables for Group Instance i2c_env_pkg.acq_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_abyte	5	0	5	100.00	100	1	1	0
cp_action	4	0	4	100.00	100	1	1	0
cp_request_type	2	0	2	100.00	100	1	1	0
cp_target_read_ack_nack	0	0	0				1	0

Crosses for Group Instance i2c_env_pkg.acq_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_abyte_X_cp_action	13	1	12	92.31	100	1	1	0

Summary for Variable cp_abyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_abyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	1009	1			T3	1		T9	1		T51	7
high	61050	1			T3	96		T9	80		T50	5
med	112767	1			T3	164		T7	4		T9	98
sml	112179	1			T3	136		T9	65		T50	6
all_zero	1208	1			T76	1		T77	2		T78	4

---

Summary for Variable cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_action

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
rstart	32643	1			T3	31		T7	2		T9	63
start	12413	1			T3	40		T7	1		T9	13
stop	12447	1			T3	40		T7	1		T9	13
none	230710	1			T3	286		T9	155		T50	8

---

Summary for Variable cp_request_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_request_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

write

6442

1

T3

18

T9

6

T50

1

read

5971

1

T3

22

T7

1

T9

7

---

Summary for Variable cp_target_read_ack_nack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	0	0	0

User Defined Bins for cp_target_read_ack_nack

Excluded/Illegal bins

NAME	COUNT	STATUS
read_req_nack_before_rstart	0	Excluded
read_req_ack_before_stop	0	Excluded
read_req_nack_before_stop	0	Excluded
read_req_ack_before_rstart	0	Excluded

---

Summary for Cross cp_abyte_X_cp_action

Samples crossed: cp_abyte cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	13	1	12	92.31	1
Automatically Generated Cross Bins	10	1	9	90.00	1
User Defined Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for cp_abyte_X_cp_action

Uncovered bins

cp_abyte	cp_action	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[stop]	0	1	1

Covered bins

cp_abyte	cp_action	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	rstart	87	1			T282	16		T283	2		T284	3
high	rstart	7149	1			T3	13		T9	37		T50	4
high	stop	2721	1			T3	7		T9	3		T76	4
med	rstart	12747	1			T3	18		T7	2		T9	26
med	stop	4773	1			T3	13		T7	1		T9	3
sml	rstart	12581	1			T76	30		T78	15		T79	1
sml	stop	4843	1			T3	20		T9	7		T76	8
all_zero	rstart	79	1			T285	8		T286	6		T287	8
all_zero	stop	110	1			T78	1		T51	3		T86	1

User Defined Cross Bins for cp_abyte_X_cp_action

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
write_address_byte	12413	1			T3	40		T7	1		T9	13
read_address_byte	12413	1			T3	40		T7	1		T9	13
data_byte	230710	1			T3	286		T9	155		T50	8