Module Definition
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Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.63 100.00 74.51 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.54 100.00 83.65 98.51 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 100.00 40.00 u_fifos


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_inp_buf 94.32 100.00 81.82 95.45 100.00
u_oup_buf 97.16 100.00 88.64 100.00 100.00
u_sram_ptrs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.63 100.00 74.51 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.54 100.00 83.65 98.51 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 100.00 40.00 u_fifos


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_inp_buf 94.32 100.00 81.82 95.45 100.00
u_oup_buf 97.16 100.00 88.64 100.00 100.00
u_sram_ptrs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.12 100.00 76.47 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.69 100.00 81.76 97.01 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 100.00 40.00 u_fifos


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_inp_buf 90.91 100.00 72.73 90.91 100.00
u_oup_buf 97.16 100.00 88.64 100.00 100.00
u_sram_ptrs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.59 100.00 82.35 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.32 100.00 86.79 98.51 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 100.00 40.00 u_fifos


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_inp_buf 94.32 100.00 81.82 95.45 100.00
u_oup_buf 97.73 100.00 90.91 100.00 100.00
u_sram_ptrs 100.00 100.00 100.00 100.00

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :
SCORELINE
93.63 100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

SCORELINE
94.12 100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

SCORELINE
93.63 100.00
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

Line No.TotalCoveredPercent
TOTAL4444100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN16211100.00
ALWAYS16433100.00
ALWAYS1742828100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
120 1 1
121 1 1
125 1 1
150 1 1
151 1 1
153 1 1
154 1 1
162 1 1
164 1 1
165 1 1
167 1 1
174 1 1
175 1 1
176 1 1
177 1 1
178 1 1
179 1 1
180 1 1
183 1 1
184 1 1
185 1 1
187 1 1
MISSING_ELSE
191 1 1
196 1 1
198 1 1
199 1 1
200 1 1
204 1 1
205 1 1
206 1 1
207 1 1
212 1 1
213 1 1
214 1 1
215 1 1
220 1 1
221 1 1
222 1 1
223 1 1
228 1 1
236 1 1
240 1 1
244 1 1
249 1 1


Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :
SCORELINE
95.59 100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

Line No.TotalCoveredPercent
TOTAL4444100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN16211100.00
ALWAYS16433100.00
ALWAYS1742828100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
120 1 1
121 1 1
125 1 1
150 1 1
151 1 1
156 1 1
157 1 1
162 1 1
164 1 1
165 1 1
167 1 1
174 1 1
175 1 1
176 1 1
177 1 1
178 1 1
179 1 1
180 1 1
183 1 1
184 1 1
185 1 1
187 1 1
MISSING_ELSE
191 1 1
196 1 1
198 1 1
199 1 1
200 1 1
204 1 1
205 1 1
206 1 1
207 1 1
212 1 1
213 1 1
214 1 1
215 1 1
220 1 1
221 1 1
222 1 1
223 1 1
228 1 1
236 1 1
240 1 1
244 1 1
249 1 1


Cond Coverage for Module : i2c_fifo_sync_sram_adapter
TotalCoveredPercent
Conditions514282.35
Logical514282.35
Non-Logical00
Event00

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T48,T103
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT159

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------
-1-StatusTests
0CoveredT159
1CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----
-1--2-StatusTests
00CoveredT159
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T21,T45
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T21,T45

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T21,T45

Branch Coverage for Module : i2c_fifo_sync_sram_adapter
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 162 2 2 100.00
IF 164 2 2 100.00
IF 183 2 2 100.00
IF 191 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 162 (clr_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 183 if (sram_read_in_prev_cyc_q)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!sram_empty)) -2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i))) -3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


Assert Coverage for Module : i2c_fifo_sync_sram_adapter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MinimalSramAw_A 6784 6784 0 0
MinimalSramFifoDepth_A 6784 6784 0 0
NoErr_A 1540520596 1539835076 0 0
NoSramReadWhenEmpty_A 1540520596 1216331335 0 0
NoSramWriteWhenFull_A 1540520596 21709627 0 0
OupBufWreadyAfterSramRead_A 1540520596 657674 0 0
SramRvalidAfterRead_A 1540520596 657674 0 0


MinimalSramAw_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6784 6784 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T7 4 4 0 0
T8 4 4 0 0
T9 4 4 0 0
T10 4 4 0 0

MinimalSramFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6784 6784 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T7 4 4 0 0
T8 4 4 0 0
T9 4 4 0 0
T10 4 4 0 0

NoErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1540520596 1539835076 0 0
T1 277792 277552 0 0
T2 552756 552408 0 0
T3 415672 415288 0 0
T4 276808 276460 0 0
T5 178836 178436 0 0
T6 42760 42408 0 0
T7 30524 30168 0 0
T8 71164 70852 0 0
T9 273332 273028 0 0
T10 307580 307368 0 0

NoSramReadWhenEmpty_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1540520596 1216331335 0 0
T1 277792 263346 0 0
T2 552756 425391 0 0
T3 415672 333905 0 0
T4 276808 235743 0 0
T5 178836 135375 0 0
T6 42760 38469 0 0
T7 30524 24012 0 0
T8 71164 60408 0 0
T9 273332 224664 0 0
T10 307580 271010 0 0

NoSramWriteWhenFull_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1540520596 21709627 0 0
T2 138189 2210 0 0
T16 0 452712 0 0
T21 325795 201037 0 0
T22 0 100672 0 0
T23 0 223075 0 0
T27 0 788537 0 0
T32 66042 0 0 0
T43 0 122017 0 0
T44 31126 0 0 0
T45 15854 0 0 0
T47 182504 0 0 0
T48 255441 0 0 0
T49 149344 104999 0 0
T52 117712 0 0 0
T58 53600 32 0 0
T59 0 1732 0 0
T60 0 7 0 0
T65 0 5 0 0
T74 0 1180 0 0
T75 0 990 0 0
T76 135658 0 0 0
T77 65708 0 0 0
T78 91127 0 0 0
T79 258652 0 0 0
T89 298883 0 0 0
T103 255822 0 0 0
T122 11889 0 0 0
T155 0 20 0 0
T160 0 18 0 0
T161 0 68808 0 0
T162 0 827763 0 0
T163 0 7 0 0
T164 0 176749 0 0
T165 0 2 0 0
T166 13060 0 0 0
T167 32299 0 0 0
T168 40871 0 0 0
T169 28757 0 0 0

OupBufWreadyAfterSramRead_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1540520596 657674 0 0
T1 69448 76 0 0
T2 276378 620 0 0
T3 415672 318 0 0
T4 276808 208 0 0
T5 178836 0 0 0
T6 42760 0 0 0
T7 30524 0 0 0
T8 71164 0 0 0
T9 273332 173 0 0
T10 307580 198 0 0
T21 651590 1538 0 0
T22 0 874 0 0
T32 0 154 0 0
T44 0 139 0 0
T46 0 50 0 0
T49 0 255 0 0
T50 28956 7 0 0
T51 0 2959 0 0
T52 0 281 0 0
T58 0 266 0 0
T76 0 380 0 0
T77 0 270 0 0
T79 0 25 0 0
T168 0 6 0 0
T170 0 53 0 0

SramRvalidAfterRead_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1540520596 657674 0 0
T1 69448 76 0 0
T2 276378 620 0 0
T3 415672 318 0 0
T4 276808 208 0 0
T5 178836 0 0 0
T6 42760 0 0 0
T7 30524 0 0 0
T8 71164 0 0 0
T9 273332 173 0 0
T10 307580 198 0 0
T21 651590 1538 0 0
T22 0 874 0 0
T32 0 154 0 0
T44 0 139 0 0
T46 0 50 0 0
T49 0 255 0 0
T50 28956 7 0 0
T51 0 2959 0 0
T52 0 281 0 0
T58 0 266 0 0
T76 0 380 0 0
T77 0 270 0 0
T79 0 25 0 0
T168 0 6 0 0
T170 0 53 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
Line No.TotalCoveredPercent
TOTAL4444100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN16211100.00
ALWAYS16433100.00
ALWAYS1742828100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
120 1 1
121 1 1
125 1 1
150 1 1
151 1 1
153 1 1
154 1 1
162 1 1
164 1 1
165 1 1
167 1 1
174 1 1
175 1 1
176 1 1
177 1 1
178 1 1
179 1 1
180 1 1
183 1 1
184 1 1
185 1 1
187 1 1
MISSING_ELSE
191 1 1
196 1 1
198 1 1
199 1 1
200 1 1
204 1 1
205 1 1
206 1 1
207 1 1
212 1 1
213 1 1
214 1 1
215 1 1
220 1 1
221 1 1
222 1 1
223 1 1
228 1 1
236 1 1
240 1 1
244 1 1
249 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
TotalCoveredPercent
Conditions513874.51
Logical513874.51
Non-Logical00
Event00

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T4,T6

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T10
11CoveredT1,T4,T6

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11CoveredT1,T4,T10

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------
-1--2-StatusTests
00CoveredT1,T4,T6
01CoveredT1,T4,T10
10Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T6

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----
-1--2-StatusTests
00Not Covered
01CoveredT1,T4,T6
10CoveredT1,T4,T10

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11CoveredT1,T4,T10

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11CoveredT1,T4,T10

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11CoveredT1,T4,T6

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11CoveredT1,T4,T6

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T10
11CoveredT1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T4,T6

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T4,T6

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T49,T22
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T49,T22

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11CoveredT21,T49,T22

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 162 2 2 100.00
IF 164 2 2 100.00
IF 183 2 2 100.00
IF 191 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 162 (clr_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 183 if (sram_read_in_prev_cyc_q)

Branches:
-1-StatusTests
1 Covered T1,T4,T10
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!sram_empty)) -2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i))) -3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T4,T10
1 0 - Covered T1,T4,T6
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MinimalSramAw_A 1696 1696 0 0
MinimalSramFifoDepth_A 1696 1696 0 0
NoErr_A 385130149 384958769 0 0
NoSramReadWhenEmpty_A 385130149 330114055 0 0
NoSramWriteWhenFull_A 385130149 21128699 0 0
OupBufWreadyAfterSramRead_A 385130149 182401 0 0
SramRvalidAfterRead_A 385130149 182401 0 0


MinimalSramAw_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1696 1696 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

MinimalSramFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1696 1696 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

NoErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 384958769 0 0
T1 69448 69388 0 0
T2 138189 138102 0 0
T3 103918 103822 0 0
T4 69202 69115 0 0
T5 44709 44609 0 0
T6 10690 10602 0 0
T7 7631 7542 0 0
T8 17791 17713 0 0
T9 68333 68257 0 0
T10 76895 76842 0 0

NoSramReadWhenEmpty_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 330114055 0 0
T1 69448 55182 0 0
T2 138189 138102 0 0
T3 103918 103822 0 0
T4 69202 28398 0 0
T5 44709 44609 0 0
T6 10690 6663 0 0
T7 7631 7542 0 0
T8 17791 7269 0 0
T9 68333 68257 0 0
T10 76895 40484 0 0

NoSramWriteWhenFull_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 21128699 0 0
T16 0 452712 0 0
T21 325795 201037 0 0
T22 0 100672 0 0
T23 0 223075 0 0
T27 0 788537 0 0
T32 66042 0 0 0
T43 0 122017 0 0
T44 31126 0 0 0
T45 15854 0 0 0
T48 255441 0 0 0
T49 149344 104999 0 0
T76 135658 0 0 0
T77 65708 0 0 0
T78 91127 0 0 0
T79 258652 0 0 0
T161 0 68808 0 0
T162 0 827763 0 0
T164 0 176749 0 0

OupBufWreadyAfterSramRead_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 182401 0 0
T1 69448 76 0 0
T2 138189 0 0 0
T3 103918 0 0 0
T4 69202 208 0 0
T5 44709 0 0 0
T6 10690 0 0 0
T7 7631 0 0 0
T8 17791 0 0 0
T9 68333 0 0 0
T10 76895 198 0 0
T21 0 1538 0 0
T22 0 874 0 0
T32 0 154 0 0
T44 0 139 0 0
T46 0 50 0 0
T49 0 255 0 0
T170 0 53 0 0

SramRvalidAfterRead_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 182401 0 0
T1 69448 76 0 0
T2 138189 0 0 0
T3 103918 0 0 0
T4 69202 208 0 0
T5 44709 0 0 0
T6 10690 0 0 0
T7 7631 0 0 0
T8 17791 0 0 0
T9 68333 0 0 0
T10 76895 198 0 0
T21 0 1538 0 0
T22 0 874 0 0
T32 0 154 0 0
T44 0 139 0 0
T46 0 50 0 0
T49 0 255 0 0
T170 0 53 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
Line No.TotalCoveredPercent
TOTAL4444100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN16211100.00
ALWAYS16433100.00
ALWAYS1742828100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
120 1 1
121 1 1
125 1 1
150 1 1
151 1 1
153 1 1
154 1 1
162 1 1
164 1 1
165 1 1
167 1 1
174 1 1
175 1 1
176 1 1
177 1 1
178 1 1
179 1 1
180 1 1
183 1 1
184 1 1
185 1 1
187 1 1
MISSING_ELSE
191 1 1
196 1 1
198 1 1
199 1 1
200 1 1
204 1 1
205 1 1
206 1 1
207 1 1
212 1 1
213 1 1
214 1 1
215 1 1
220 1 1
221 1 1
222 1 1
223 1 1
228 1 1
236 1 1
240 1 1
244 1 1
249 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
TotalCoveredPercent
Conditions513874.51
Logical513874.51
Non-Logical00
Event00

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T7,T9

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT3,T7,T9

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T9
11CoveredT3,T7,T9

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T9
11CoveredT3,T7,T9

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------
-1--2-StatusTests
00CoveredT3,T7,T9
01CoveredT3,T7,T9
10Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------
-1-StatusTests
0Not Covered
1CoveredT3,T7,T9

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----
-1--2-StatusTests
00Not Covered
01CoveredT3,T7,T9
10CoveredT3,T7,T9

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T7,T9
11CoveredT3,T7,T9

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T7,T9
11CoveredT3,T7,T9

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T7,T9
11CoveredT3,T7,T9

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT3,T7,T9
11CoveredT3,T7,T9

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T9
11CoveredT1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T7,T9

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T7,T9

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT171,T104,T94
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT171,T104,T94

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----
-1--2-StatusTests
01CoveredT3,T7,T9
10Not Covered
11CoveredT171,T104,T94

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 162 2 2 100.00
IF 164 2 2 100.00
IF 183 2 2 100.00
IF 191 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 162 (clr_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 183 if (sram_read_in_prev_cyc_q)

Branches:
-1-StatusTests
1 Covered T3,T7,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!sram_empty)) -2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i))) -3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:
-1--2--3-StatusTests
1 1 - Covered T3,T7,T9
1 0 - Covered T3,T7,T9
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MinimalSramAw_A 1696 1696 0 0
MinimalSramFifoDepth_A 1696 1696 0 0
NoErr_A 385130149 384958769 0 0
NoSramReadWhenEmpty_A 385130149 364316100 0 0
NoSramWriteWhenFull_A 385130149 265693 0 0
OupBufWreadyAfterSramRead_A 385130149 110032 0 0
SramRvalidAfterRead_A 385130149 110032 0 0


MinimalSramAw_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1696 1696 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

MinimalSramFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1696 1696 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

NoErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 384958769 0 0
T1 69448 69388 0 0
T2 138189 138102 0 0
T3 103918 103822 0 0
T4 69202 69115 0 0
T5 44709 44609 0 0
T6 10690 10602 0 0
T7 7631 7542 0 0
T8 17791 17713 0 0
T9 68333 68257 0 0
T10 76895 76842 0 0

NoSramReadWhenEmpty_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 364316100 0 0
T1 69448 69388 0 0
T2 138189 138102 0 0
T3 103918 67794 0 0
T4 69202 69115 0 0
T5 44709 44609 0 0
T6 10690 10602 0 0
T7 7631 1386 0 0
T8 17791 17713 0 0
T9 68333 42249 0 0
T10 76895 76842 0 0

NoSramWriteWhenFull_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 265693 0 0
T25 52163 0 0 0
T53 0 9954 0 0
T54 0 6248 0 0
T55 0 10038 0 0
T94 0 66 0 0
T104 0 439 0 0
T171 16353 146 0 0
T172 0 569 0 0
T173 0 9448 0 0
T174 0 337 0 0
T175 0 8594 0 0
T176 50136 0 0 0
T177 8792 0 0 0
T178 50943 0 0 0
T179 103731 0 0 0
T180 356880 0 0 0
T181 86644 0 0 0
T182 4738 0 0 0
T183 154977 0 0 0

OupBufWreadyAfterSramRead_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 110032 0 0
T3 103918 228 0 0
T4 69202 0 0 0
T5 44709 0 0 0
T6 10690 0 0 0
T7 7631 38 0 0
T8 17791 0 0 0
T9 68333 200 0 0
T10 76895 0 0 0
T21 325795 0 0 0
T50 9652 9 0 0
T51 0 1019 0 0
T76 0 159 0 0
T77 0 159 0 0
T78 0 282 0 0
T79 0 10 0 0
T80 0 81 0 0

SramRvalidAfterRead_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 110032 0 0
T3 103918 228 0 0
T4 69202 0 0 0
T5 44709 0 0 0
T6 10690 0 0 0
T7 7631 38 0 0
T8 17791 0 0 0
T9 68333 200 0 0
T10 76895 0 0 0
T21 325795 0 0 0
T50 9652 9 0 0
T51 0 1019 0 0
T76 0 159 0 0
T77 0 159 0 0
T78 0 282 0 0
T79 0 10 0 0
T80 0 81 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
Line No.TotalCoveredPercent
TOTAL4444100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN16211100.00
ALWAYS16433100.00
ALWAYS1742828100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
120 1 1
121 1 1
125 1 1
150 1 1
151 1 1
153 1 1
154 1 1
162 1 1
164 1 1
165 1 1
167 1 1
174 1 1
175 1 1
176 1 1
177 1 1
178 1 1
179 1 1
180 1 1
183 1 1
184 1 1
185 1 1
187 1 1
MISSING_ELSE
191 1 1
196 1 1
198 1 1
199 1 1
200 1 1
204 1 1
205 1 1
206 1 1
207 1 1
212 1 1
213 1 1
214 1 1
215 1 1
220 1 1
221 1 1
222 1 1
223 1 1
228 1 1
236 1 1
240 1 1
244 1 1
249 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
TotalCoveredPercent
Conditions513976.47
Logical513976.47
Non-Logical00
Event00

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T48,T103
11CoveredT1,T2,T4

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT2,T45,T48

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T48,T103
11CoveredT2,T45,T48

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T45,T48
11CoveredT2,T48,T103

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------
-1--2-StatusTests
00CoveredT2,T45,T48
01CoveredT2,T48,T103
10Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------
-1-StatusTests
0Not Covered
1CoveredT2,T45,T48

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----
-1--2-StatusTests
00Not Covered
01CoveredT2,T45,T48
10CoveredT2,T48,T103

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT2,T45,T48
11CoveredT2,T48,T103

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT2,T45,T48
11CoveredT2,T48,T103

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT2,T45,T48
11CoveredT2,T45,T48

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT2,T45,T48
11CoveredT2,T45,T48

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T48,T103
11CoveredT1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T45,T48

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T45,T48

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T45,T48
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T45,T48

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----
-1--2-StatusTests
01CoveredT2,T45,T48
10Not Covered
11CoveredT2,T45,T48

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 162 2 2 100.00
IF 164 2 2 100.00
IF 183 2 2 100.00
IF 191 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 162 (clr_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 183 if (sram_read_in_prev_cyc_q)

Branches:
-1-StatusTests
1 Covered T2,T48,T103
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!sram_empty)) -2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i))) -3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:
-1--2--3-StatusTests
1 1 - Covered T2,T48,T103
1 0 - Covered T2,T45,T48
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MinimalSramAw_A 1696 1696 0 0
MinimalSramFifoDepth_A 1696 1696 0 0
NoErr_A 385130149 384958769 0 0
NoSramReadWhenEmpty_A 385130149 359365511 0 0
NoSramWriteWhenFull_A 385130149 253029 0 0
OupBufWreadyAfterSramRead_A 385130149 127286 0 0
SramRvalidAfterRead_A 385130149 127286 0 0


MinimalSramAw_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1696 1696 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

MinimalSramFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1696 1696 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

NoErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 384958769 0 0
T1 69448 69388 0 0
T2 138189 138102 0 0
T3 103918 103822 0 0
T4 69202 69115 0 0
T5 44709 44609 0 0
T6 10690 10602 0 0
T7 7631 7542 0 0
T8 17791 17713 0 0
T9 68333 68257 0 0
T10 76895 76842 0 0

NoSramReadWhenEmpty_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 359365511 0 0
T1 69448 69388 0 0
T2 138189 11085 0 0
T3 103918 103822 0 0
T4 69202 69115 0 0
T5 44709 44609 0 0
T6 10690 10602 0 0
T7 7631 7542 0 0
T8 17791 17713 0 0
T9 68333 68257 0 0
T10 76895 76842 0 0

NoSramWriteWhenFull_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 253029 0 0
T2 138189 2210 0 0
T3 103918 0 0 0
T4 69202 0 0 0
T5 44709 0 0 0
T6 10690 0 0 0
T7 7631 0 0 0
T8 17791 0 0 0
T9 68333 0 0 0
T10 76895 0 0 0
T33 0 1078 0 0
T39 0 3523 0 0
T45 0 4 0 0
T48 0 4125 0 0
T50 9652 0 0 0
T89 0 567 0 0
T90 0 178 0 0
T103 0 4074 0 0
T122 0 3 0 0
T126 0 3537 0 0

OupBufWreadyAfterSramRead_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 127286 0 0
T2 138189 620 0 0
T3 103918 0 0 0
T4 69202 0 0 0
T5 44709 0 0 0
T6 10690 0 0 0
T7 7631 0 0 0
T8 17791 0 0 0
T9 68333 0 0 0
T10 76895 0 0 0
T15 0 2666 0 0
T33 0 1178 0 0
T39 0 1116 0 0
T48 0 1240 0 0
T50 9652 0 0 0
T89 0 682 0 0
T90 0 1054 0 0
T103 0 1116 0 0
T126 0 1178 0 0
T184 0 930 0 0

SramRvalidAfterRead_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 127286 0 0
T2 138189 620 0 0
T3 103918 0 0 0
T4 69202 0 0 0
T5 44709 0 0 0
T6 10690 0 0 0
T7 7631 0 0 0
T8 17791 0 0 0
T9 68333 0 0 0
T10 76895 0 0 0
T15 0 2666 0 0
T33 0 1178 0 0
T39 0 1116 0 0
T48 0 1240 0 0
T50 9652 0 0 0
T89 0 682 0 0
T90 0 1054 0 0
T103 0 1116 0 0
T126 0 1178 0 0
T184 0 930 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
Line No.TotalCoveredPercent
TOTAL4444100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN16211100.00
ALWAYS16433100.00
ALWAYS1742828100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
120 1 1
121 1 1
125 1 1
150 1 1
151 1 1
156 1 1
157 1 1
162 1 1
164 1 1
165 1 1
167 1 1
174 1 1
175 1 1
176 1 1
177 1 1
178 1 1
179 1 1
180 1 1
183 1 1
184 1 1
185 1 1
187 1 1
MISSING_ELSE
191 1 1
196 1 1
198 1 1
199 1 1
200 1 1
204 1 1
205 1 1
206 1 1
207 1 1
212 1 1
213 1 1
214 1 1
215 1 1
220 1 1
221 1 1
222 1 1
223 1 1
228 1 1
236 1 1
240 1 1
244 1 1
249 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
TotalCoveredPercent
Conditions514282.35
Logical514282.35
Non-Logical00
Event00

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT56,T57
11CoveredT3,T5,T7

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT3,T5,T9

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T9,T50
11CoveredT3,T5,T9

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T9
11CoveredT3,T9,T50

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------
-1--2-StatusTests
00CoveredT3,T5,T9
01CoveredT3,T9,T50
10CoveredT159

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------
-1-StatusTests
0CoveredT159
1CoveredT3,T5,T9

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----
-1--2-StatusTests
00CoveredT159
01CoveredT3,T5,T9
10CoveredT3,T9,T50

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T5,T9
11CoveredT3,T9,T50

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T5,T9
11CoveredT3,T9,T50

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T5,T9
11CoveredT3,T5,T9

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT3,T5,T9
11CoveredT3,T5,T9

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T9,T50
11CoveredT1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T5,T9

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T5,T9

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT58,T59,T60
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT58,T59,T60

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----
-1--2-StatusTests
01CoveredT3,T5,T9
10Not Covered
11CoveredT58,T59,T60

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 162 2 2 100.00
IF 164 2 2 100.00
IF 183 2 2 100.00
IF 191 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 162 (clr_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 183 if (sram_read_in_prev_cyc_q)

Branches:
-1-StatusTests
1 Covered T3,T9,T50
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!sram_empty)) -2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i))) -3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:
-1--2--3-StatusTests
1 1 - Covered T3,T9,T50
1 0 - Covered T3,T5,T9
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MinimalSramAw_A 1696 1696 0 0
MinimalSramFifoDepth_A 1696 1696 0 0
NoErr_A 385130149 384958769 0 0
NoSramReadWhenEmpty_A 385130149 162535669 0 0
NoSramWriteWhenFull_A 385130149 62206 0 0
OupBufWreadyAfterSramRead_A 385130149 237955 0 0
SramRvalidAfterRead_A 385130149 237955 0 0


MinimalSramAw_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1696 1696 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

MinimalSramFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1696 1696 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

NoErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 384958769 0 0
T1 69448 69388 0 0
T2 138189 138102 0 0
T3 103918 103822 0 0
T4 69202 69115 0 0
T5 44709 44609 0 0
T6 10690 10602 0 0
T7 7631 7542 0 0
T8 17791 17713 0 0
T9 68333 68257 0 0
T10 76895 76842 0 0

NoSramReadWhenEmpty_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 162535669 0 0
T1 69448 69388 0 0
T2 138189 138102 0 0
T3 103918 58467 0 0
T4 69202 69115 0 0
T5 44709 1548 0 0
T6 10690 10602 0 0
T7 7631 7542 0 0
T8 17791 17713 0 0
T9 68333 45901 0 0
T10 76895 76842 0 0

NoSramWriteWhenFull_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 62206 0 0
T47 182504 0 0 0
T52 117712 0 0 0
T58 53600 32 0 0
T59 0 1732 0 0
T60 0 7 0 0
T65 0 5 0 0
T74 0 1180 0 0
T75 0 990 0 0
T89 298883 0 0 0
T103 255822 0 0 0
T122 11889 0 0 0
T155 0 20 0 0
T160 0 18 0 0
T163 0 7 0 0
T165 0 2 0 0
T166 13060 0 0 0
T167 32299 0 0 0
T168 40871 0 0 0
T169 28757 0 0 0

OupBufWreadyAfterSramRead_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 237955 0 0
T3 103918 318 0 0
T4 69202 0 0 0
T5 44709 0 0 0
T6 10690 0 0 0
T7 7631 0 0 0
T8 17791 0 0 0
T9 68333 173 0 0
T10 76895 0 0 0
T21 325795 0 0 0
T50 9652 7 0 0
T51 0 2959 0 0
T52 0 281 0 0
T58 0 266 0 0
T76 0 380 0 0
T77 0 270 0 0
T79 0 25 0 0
T168 0 6 0 0

SramRvalidAfterRead_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385130149 237955 0 0
T3 103918 318 0 0
T4 69202 0 0 0
T5 44709 0 0 0
T6 10690 0 0 0
T7 7631 0 0 0
T8 17791 0 0 0
T9 68333 173 0 0
T10 76895 0 0 0
T21 325795 0 0 0
T50 9652 7 0 0
T51 0 2959 0 0
T52 0 281 0 0
T58 0 266 0 0
T76 0 380 0 0
T77 0 270 0 0
T79 0 25 0 0
T168 0 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%