Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	385793983	0	0	0
ctrl_rd_A	385793983	2378	0	0
host_fifo_config_rd_A	385793983	4096	0	0
host_nack_handler_timeout_rd_A	385793983	1606	0	0
host_timeout_ctrl_rd_A	385793983	1358	0	0
intr_enable_rd_A	385793983	3818	0	0
ovrd_rd_A	385793983	2133	0	0
target_fifo_config_rd_A	385793983	1538	0	0
target_id_rd_A	385793983	1671	0	0
target_timeout_ctrl_rd_A	385793983	1446	0	0
timeout_ctrl_rd_A	385793983	1759	0	0
timing0_rd_A	385793983	1516	0	0
timing1_rd_A	385793983	1424	0	0
timing2_rd_A	385793983	1443	0	0
timing3_rd_A	385793983	1640	0	0
timing4_rd_A	385793983	1424	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	2378	0	0
T105	3054	40	0	0
T106	5922	118	0	0
T107	12661	17	0	0
T108	5636	77	0	0
T109	6770	26	0	0
T110	7034	163	0	0
T111	3412	2	0	0
T112	7668	14	0	0
T113	3444	5	0	0
T114	2383	15	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	4096	0	0
T33	514778	192	0	0
T47	182504	0	0	0
T59	55966	0	0	0
T86	152467	0	0	0
T89	298883	147	0	0
T96	0	61	0	0
T115	0	133	0	0
T116	0	359	0	0
T117	0	75	0	0
T118	0	70	0	0
T119	0	235	0	0
T120	0	64	0	0
T121	0	217	0	0
T122	11889	0	0	0
T123	13749	0	0	0
T124	14481	0	0	0
T125	10436	0	0	0
T126	231381	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1606	0	0
T105	3054	28	0	0
T106	5922	115	0	0
T107	12661	14	0	0
T108	5636	45	0	0
T109	6770	29	0	0
T110	7034	44	0	0
T111	3412	34	0	0
T112	7668	3	0	0
T113	3444	13	0	0
T114	2383	15	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1358	0	0
T105	3054	19	0	0
T106	5922	112	0	0
T107	12661	30	0	0
T108	5636	58	0	0
T109	6770	37	0	0
T110	7034	27	0	0
T111	3412	31	0	0
T112	7668	13	0	0
T113	3444	5	0	0
T114	2383	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	3818	0	0
T37	941948	18	0	0
T105	0	144	0	0
T106	0	108	0	0
T107	0	22	0	0
T108	0	15	0	0
T109	0	44	0	0
T110	0	203	0	0
T127	0	43	0	0
T128	0	59	0	0
T129	0	35	0	0
T130	88810	0	0	0
T131	8336	0	0	0
T132	16320	0	0	0
T133	123675	0	0	0
T134	1041	0	0	0
T135	58946	0	0	0
T136	1032	0	0	0
T137	140641	0	0	0
T138	14282	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	2133	0	0
T72	72430	0	0	0
T139	1440	71	0	0
T140	0	53	0	0
T141	0	17	0	0
T142	0	44	0	0
T143	0	22	0	0
T144	0	15	0	0
T145	0	40	0	0
T146	0	9	0	0
T147	0	21	0	0
T148	0	61	0	0
T149	12516	0	0	0
T150	7043	0	0	0
T151	1376	0	0	0
T152	13071	0	0	0
T153	9189	0	0	0
T154	497756	0	0	0
T155	60244	0	0	0
T156	20593	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1538	0	0
T105	3054	40	0	0
T106	5922	116	0	0
T107	12661	54	0	0
T108	5636	41	0	0
T109	6770	15	0	0
T110	7034	68	0	0
T111	3412	7	0	0
T112	7668	17	0	0
T113	3444	20	0	0
T114	2383	14	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1671	0	0
T105	3054	11	0	0
T106	5922	117	0	0
T107	12661	27	0	0
T108	5636	69	0	0
T109	6770	29	0	0
T110	7034	83	0	0
T112	7668	24	0	0
T113	3444	11	0	0
T114	2383	5	0	0
T157	7686	70	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1446	0	0
T105	3054	11	0	0
T106	5922	131	0	0
T107	12661	19	0	0
T108	5636	33	0	0
T109	6770	24	0	0
T110	7034	72	0	0
T111	3412	22	0	0
T112	7668	14	0	0
T113	3444	17	0	0
T114	2383	3	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1759	0	0
T105	3054	11	0	0
T106	5922	100	0	0
T107	12661	29	0	0
T108	5636	68	0	0
T109	6770	13	0	0
T110	7034	83	0	0
T111	3412	29	0	0
T112	7668	43	0	0
T113	3444	13	0	0
T114	2383	4	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1516	0	0
T105	3054	34	0	0
T106	5922	117	0	0
T107	12661	19	0	0
T108	5636	18	0	0
T109	6770	11	0	0
T110	7034	67	0	0
T111	3412	42	0	0
T112	7668	6	0	0
T113	3444	8	0	0
T114	2383	4	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1424	0	0
T105	3054	23	0	0
T106	5922	99	0	0
T107	12661	28	0	0
T108	5636	67	0	0
T110	7034	68	0	0
T111	3412	13	0	0
T112	7668	2	0	0
T113	3444	5	0	0
T157	7686	84	0	0
T158	6491	30	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1443	0	0
T105	3054	24	0	0
T106	5922	123	0	0
T107	12661	35	0	0
T108	5636	64	0	0
T109	6770	21	0	0
T110	7034	47	0	0
T111	3412	33	0	0
T112	7668	7	0	0
T114	2383	2	0	0
T157	7686	56	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1640	0	0
T105	3054	19	0	0
T106	5922	110	0	0
T107	12661	39	0	0
T108	5636	56	0	0
T109	6770	13	0	0
T110	7034	46	0	0
T111	3412	30	0	0
T112	7668	5	0	0
T113	3444	21	0	0
T114	2383	11	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385793983	1424	0	0
T105	3054	15	0	0
T106	5922	102	0	0
T107	12661	32	0	0
T108	5636	38	0	0
T109	6770	25	0	0
T110	7034	74	0	0
T111	3412	12	0	0
T112	7668	3	0	0
T113	3444	37	0	0
T114	2383	2	0	0