Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	771878	1			T1	2308		T2	3		T3	4174
all_values[1]	771878	1			T1	2308		T2	3		T3	4174
all_values[2]	771878	1			T1	2308		T2	3		T3	4174
all_values[3]	771878	1			T1	2308		T2	3		T3	4174
all_values[4]	771878	1			T1	2308		T2	3		T3	4174
all_values[5]	771878	1			T1	2308		T2	3		T3	4174
all_values[6]	771878	1			T1	2308		T2	3		T3	4174
all_values[7]	771878	1			T1	2308		T2	3		T3	4174
all_values[8]	771878	1			T1	2308		T2	3		T3	4174
all_values[9]	771878	1			T1	2308		T2	3		T3	4174
all_values[10]	771878	1			T1	2308		T2	3		T3	4174
all_values[11]	771878	1			T1	2308		T2	3		T3	4174
all_values[12]	771878	1			T1	2308		T2	3		T3	4174
all_values[13]	771878	1			T1	2308		T2	3		T3	4174
all_values[14]	771878	1			T1	2308		T2	3		T3	4174

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9517593

1

T1

31354

T2

39

T3

54268

auto[1]

2060577

1

T1

3266

T2

6

T3

8342

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11096816

1

T1

34620

T2

45

T3

62610

auto[1]

481354

1

T16

4759

T105

272521

T178

158

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98320	1			T1	1474		T2	1		T3	3
all_values[0]	auto[0]	auto[1]	6060	1			T16	39		T105	3713		T178	7
all_values[0]	auto[1]	auto[0]	641696	1			T1	834		T2	2		T3	4171
all_values[0]	auto[1]	auto[1]	25802	1			T16	280		T105	14455		T178	5
all_values[1]	auto[0]	auto[0]	738994	1			T1	2308		T2	3		T3	4174
all_values[1]	auto[0]	auto[1]	32317	1			T16	316		T105	18163		T178	6
all_values[1]	auto[1]	auto[0]	429	1			T254	64		T255	8		T256	20
all_values[1]	auto[1]	auto[1]	138	1			T16	3		T105	6		T178	1
all_values[2]	auto[0]	auto[0]	739241	1			T1	2308		T2	3		T3	4174
all_values[2]	auto[0]	auto[1]	32317	1			T16	311		T105	18165		T178	9
all_values[2]	auto[1]	auto[0]	190	1			T9	2		T157	1		T46	2
all_values[2]	auto[1]	auto[1]	130	1			T16	3		T105	2		T178	3
all_values[3]	auto[0]	auto[0]	739432	1			T1	2308		T2	3		T3	4174
all_values[3]	auto[0]	auto[1]	32286	1			T16	310		T105	18164		T178	8
all_values[3]	auto[1]	auto[1]	160	1			T16	4		T105	3		T178	3
all_values[4]	auto[0]	auto[0]	739440	1			T1	2308		T2	3		T3	4174
all_values[4]	auto[0]	auto[1]	32287	1			T16	315		T105	18163		T178	7
all_values[4]	auto[1]	auto[0]	9	1			T235	1		T257	1		T243	1
all_values[4]	auto[1]	auto[1]	142	1			T16	4		T105	5		T178	2
all_values[5]	auto[0]	auto[0]	739408	1			T1	2308		T2	3		T3	4174
all_values[5]	auto[0]	auto[1]	32307	1			T16	313		T105	18165		T178	11
all_values[5]	auto[1]	auto[1]	163	1			T16	6		T105	4		T226	3
all_values[6]	auto[0]	auto[0]	743093	1			T1	2308		T2	3		T3	4174
all_values[6]	auto[0]	auto[1]	28632	1			T16	314		T105	18166		T178	7
all_values[6]	auto[1]	auto[1]	153	1			T16	4		T105	3		T178	2
all_values[7]	auto[0]	auto[0]	711198	1			T1	2182		T2	2		T3	4174
all_values[7]	auto[0]	auto[1]	30938	1			T16	278		T105	17807		T178	8
all_values[7]	auto[1]	auto[0]	28233	1			T1	126		T2	1		T5	1
all_values[7]	auto[1]	auto[1]	1509	1			T16	41		T105	361		T178	3
all_values[8]	auto[0]	auto[0]	739433	1			T1	2308		T2	3		T3	4174
all_values[8]	auto[0]	auto[1]	32292	1			T16	315		T105	18164		T178	6
all_values[8]	auto[1]	auto[1]	153	1			T16	4		T105	4		T178	6
all_values[9]	auto[0]	auto[0]	163127	1			T1	2305		T2	2		T3	4174
all_values[9]	auto[0]	auto[1]	16962	1			T16	296		T105	13376		T178	7
all_values[9]	auto[1]	auto[0]	576272	1			T1	3		T2	1		T5	1
all_values[9]	auto[1]	auto[1]	15517	1			T16	23		T105	4792		T178	5
all_values[10]	auto[0]	auto[0]	739410	1			T1	2308		T2	3		T3	4174
all_values[10]	auto[0]	auto[1]	32317	1			T16	317		T105	18163		T178	6
all_values[10]	auto[1]	auto[1]	151	1			T16	1		T105	5		T178	3
all_values[11]	auto[0]	auto[0]	2342	1			T1	5		T2	1		T3	3
all_values[11]	auto[0]	auto[1]	323	1			T16	37		T105	23		T178	4
all_values[11]	auto[1]	auto[0]	737094	1			T1	2303		T2	2		T3	4171
all_values[11]	auto[1]	auto[1]	32119	1			T16	280		T105	18144		T178	6
all_values[12]	auto[0]	auto[0]	739965	1			T1	2308		T2	3		T3	4174
all_values[12]	auto[0]	auto[1]	31702	1			T16	313		T105	18163		T178	7
all_values[12]	auto[1]	auto[0]	61	1			T46	2		T47	1		T258	1
all_values[12]	auto[1]	auto[1]	150	1			T16	1		T105	6		T178	4
all_values[13]	auto[0]	auto[0]	740024	1			T1	2308		T2	3		T3	4174
all_values[13]	auto[0]	auto[1]	31689	1			T16	310		T105	18161		T178	9
all_values[13]	auto[1]	auto[1]	165	1			T16	2		T105	6		T178	2
all_values[14]	auto[0]	auto[0]	739405	1			T1	2308		T2	3		T3	4174
all_values[14]	auto[0]	auto[1]	32332	1			T16	315		T105	18164		T178	11
all_values[14]	auto[1]	auto[1]	141	1			T16	4		T105	5		T226	1