Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	771878	1			T1	2308		T2	3		T3	4174
all_pins[1]	771878	1			T1	2308		T2	3		T3	4174
all_pins[2]	771878	1			T1	2308		T2	3		T3	4174
all_pins[3]	771878	1			T1	2308		T2	3		T3	4174
all_pins[4]	771878	1			T1	2308		T2	3		T3	4174
all_pins[5]	771878	1			T1	2308		T2	3		T3	4174
all_pins[6]	771878	1			T1	2308		T2	3		T3	4174
all_pins[7]	771878	1			T1	2308		T2	3		T3	4174
all_pins[8]	771878	1			T1	2308		T2	3		T3	4174
all_pins[9]	771878	1			T1	2308		T2	3		T3	4174
all_pins[10]	771878	1			T1	2308		T2	3		T3	4174
all_pins[11]	771878	1			T1	2308		T2	3		T3	4174
all_pins[12]	771878	1			T1	2308		T2	3		T3	4174
all_pins[13]	771878	1			T1	2308		T2	3		T3	4174
all_pins[14]	771878	1			T1	2308		T2	3		T3	4174

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9523415	1			T1	31354		T2	39		T3	54268
values[0x1]	2054755	1			T1	3266		T2	6		T3	8342
transitions[0x0=>0x1]	2053914	1			T1	3266		T2	6		T3	8342
transitions[0x1=>0x0]	2052605	1			T1	3265		T2	5		T3	8341

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	108018	1			T1	1474		T2	1		T3	3
all_pins[0]	values[0x1]	663860	1			T1	834		T2	2		T3	4171
all_pins[0]	transitions[0x0=>0x1]	663313	1			T1	834		T2	2		T3	4171
all_pins[0]	transitions[0x1=>0x0]	52	1			T16	2		T105	3		T178	1
all_pins[1]	values[0x0]	771279	1			T1	2308		T2	3		T3	4174
all_pins[1]	values[0x1]	599	1			T254	77		T255	10		T16	3
all_pins[1]	transitions[0x0=>0x1]	583	1			T254	77		T255	10		T16	2
all_pins[1]	transitions[0x1=>0x0]	100	1			T157	1		T258	1		T264	1
all_pins[2]	values[0x0]	771762	1			T1	2308		T2	3		T3	4174
all_pins[2]	values[0x1]	116	1			T157	1		T258	1		T264	1
all_pins[2]	transitions[0x0=>0x1]	100	1			T157	1		T258	1		T264	1
all_pins[2]	transitions[0x1=>0x0]	53	1			T16	1		T105	2		T178	3
all_pins[3]	values[0x0]	771809	1			T1	2308		T2	3		T3	4174
all_pins[3]	values[0x1]	69	1			T16	2		T105	2		T178	3
all_pins[3]	transitions[0x0=>0x1]	59	1			T16	2		T105	2		T178	3
all_pins[3]	transitions[0x1=>0x0]	76	1			T16	1		T105	3		T178	1
all_pins[4]	values[0x0]	771792	1			T1	2308		T2	3		T3	4174
all_pins[4]	values[0x1]	86	1			T16	1		T105	3		T178	1
all_pins[4]	transitions[0x0=>0x1]	66	1			T16	1		T105	3		T178	1
all_pins[4]	transitions[0x1=>0x0]	64	1			T16	4		T105	4		T226	3
all_pins[5]	values[0x0]	771794	1			T1	2308		T2	3		T3	4174
all_pins[5]	values[0x1]	84	1			T16	4		T105	4		T226	3
all_pins[5]	transitions[0x0=>0x1]	62	1			T16	4		T105	4		T226	2
all_pins[5]	transitions[0x1=>0x0]	57	1			T16	1		T105	1		T178	1
all_pins[6]	values[0x0]	771799	1			T1	2308		T2	3		T3	4174
all_pins[6]	values[0x1]	79	1			T16	1		T105	1		T178	1
all_pins[6]	transitions[0x0=>0x1]	55	1			T105	1		T226	2		T265	4
all_pins[6]	transitions[0x1=>0x0]	32491	1			T1	126		T2	1		T5	1
all_pins[7]	values[0x0]	739363	1			T1	2182		T2	2		T3	4174
all_pins[7]	values[0x1]	32515	1			T1	126		T2	1		T5	1
all_pins[7]	transitions[0x0=>0x1]	32488	1			T1	126		T2	1		T5	1
all_pins[7]	transitions[0x1=>0x0]	46	1			T105	1		T178	4		T114	1
all_pins[8]	values[0x0]	771805	1			T1	2308		T2	3		T3	4174
all_pins[8]	values[0x1]	73	1			T16	1		T105	1		T178	5
all_pins[8]	transitions[0x0=>0x1]	54	1			T16	1		T178	4		T114	2
all_pins[8]	transitions[0x1=>0x0]	591703	1			T1	3		T2	1		T5	1
all_pins[9]	values[0x0]	180156	1			T1	2305		T2	2		T3	4174
all_pins[9]	values[0x1]	591722	1			T1	3		T2	1		T5	1
all_pins[9]	transitions[0x0=>0x1]	591704	1			T1	3		T2	1		T5	1
all_pins[9]	transitions[0x1=>0x0]	72	1			T16	1		T105	1		T178	2
all_pins[10]	values[0x0]	771788	1			T1	2308		T2	3		T3	4174
all_pins[10]	values[0x1]	90	1			T16	1		T105	1		T178	2
all_pins[10]	transitions[0x0=>0x1]	61	1			T16	1		T105	1		T178	1
all_pins[10]	transitions[0x1=>0x0]	765142	1			T1	2303		T2	2		T3	4171
all_pins[11]	values[0x0]	6707	1			T1	5		T2	1		T3	3
all_pins[11]	values[0x1]	765171	1			T1	2303		T2	2		T3	4171
all_pins[11]	transitions[0x0=>0x1]	765134	1			T1	2303		T2	2		T3	4171
all_pins[11]	transitions[0x1=>0x0]	101	1			T46	2		T47	1		T61	1
all_pins[12]	values[0x0]	771740	1			T1	2308		T2	3		T3	4174
all_pins[12]	values[0x1]	138	1			T46	2		T47	1		T258	1
all_pins[12]	transitions[0x0=>0x1]	125	1			T46	2		T47	1		T258	1
all_pins[12]	transitions[0x1=>0x0]	71	1			T16	2		T105	3		T226	3
all_pins[13]	values[0x0]	771794	1			T1	2308		T2	3		T3	4174
all_pins[13]	values[0x1]	84	1			T16	2		T105	3		T226	3
all_pins[13]	transitions[0x0=>0x1]	65	1			T16	2		T105	3		T226	3
all_pins[13]	transitions[0x1=>0x0]	50	1			T16	2		T105	2		T226	1
all_pins[14]	values[0x0]	771809	1			T1	2308		T2	3		T3	4174
all_pins[14]	values[0x1]	69	1			T16	2		T105	2		T226	1
all_pins[14]	transitions[0x0=>0x1]	45	1			T16	2		T105	1		T226	1
all_pins[14]	transitions[0x1=>0x0]	662527	1			T1	833		T2	1		T3	4170