Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	352	1			T16	8		T105	11		T178	7
all_values[1]	352	1			T16	8		T105	11		T178	7
all_values[2]	352	1			T16	8		T105	11		T178	7
all_values[3]	352	1			T16	8		T105	11		T178	7
all_values[4]	352	1			T16	8		T105	11		T178	7
all_values[5]	352	1			T16	8		T105	11		T178	7
all_values[6]	352	1			T16	8		T105	11		T178	7
all_values[7]	352	1			T16	8		T105	11		T178	7
all_values[8]	352	1			T16	8		T105	11		T178	7
all_values[9]	352	1			T16	8		T105	11		T178	7
all_values[10]	352	1			T16	8		T105	11		T178	7
all_values[11]	352	1			T16	8		T105	11		T178	7
all_values[12]	352	1			T16	8		T105	11		T178	7
all_values[13]	352	1			T16	8		T105	11		T178	7
all_values[14]	352	1			T16	8		T105	11		T178	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2858

1

T16

63

T105

101

T178

59

auto[1]

2422

1

T16

57

T105

64

T178

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

864

1

T16

22

T105

14

T178

22

auto[1]

4416

1

T16

98

T105

151

T178

83

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3150

1

T16

75

T105

99

T178

63

auto[1]

2130

1

T16

45

T105

66

T178

42

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	41	1			T105	1		T265	4		T266	1
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T16	2		T105	1		T178	2
all_values[0]	auto[0]	auto[1]	auto[0]	13	1			T267	2		T268	2		T269	1
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T16	2		T105	4		T178	3
all_values[0]	auto[1]	auto[0]	auto[1]	88	1			T16	1		T105	4		T178	2
all_values[0]	auto[1]	auto[1]	auto[1]	61	1			T16	3		T105	1		T226	2
all_values[1]	auto[0]	auto[0]	auto[0]	37	1			T178	4		T226	2		T268	1
all_values[1]	auto[0]	auto[0]	auto[1]	70	1			T16	1		T105	3		T226	1
all_values[1]	auto[0]	auto[1]	auto[0]	21	1			T178	1		T226	2		T268	3
all_values[1]	auto[0]	auto[1]	auto[1]	86	1			T16	4		T105	2		T178	1
all_values[1]	auto[1]	auto[0]	auto[1]	74	1			T16	1		T105	4		T226	2
all_values[1]	auto[1]	auto[1]	auto[1]	64	1			T16	2		T105	2		T178	1
all_values[2]	auto[0]	auto[0]	auto[0]	39	1			T16	3		T105	2		T114	1
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T105	5		T178	2		T226	1
all_values[2]	auto[0]	auto[1]	auto[0]	25	1			T16	1		T115	3		T270	2
all_values[2]	auto[0]	auto[1]	auto[1]	79	1			T16	1		T105	2		T178	2
all_values[2]	auto[1]	auto[0]	auto[1]	70	1			T16	1		T105	2		T178	2
all_values[2]	auto[1]	auto[1]	auto[1]	60	1			T16	2		T178	1		T226	3
all_values[3]	auto[0]	auto[0]	auto[0]	47	1			T16	2		T105	1		T178	1
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T105	2		T114	4		T265	2
all_values[3]	auto[0]	auto[1]	auto[0]	20	1			T16	2		T105	1		T226	1
all_values[3]	auto[0]	auto[1]	auto[1]	78	1			T16	1		T105	4		T178	2
all_values[3]	auto[1]	auto[0]	auto[1]	70	1			T16	3		T105	2		T226	2
all_values[3]	auto[1]	auto[1]	auto[1]	58	1			T105	1		T178	4		T226	2
all_values[4]	auto[0]	auto[0]	auto[0]	54	1			T105	1		T178	3		T114	1
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T16	2		T105	3		T114	4
all_values[4]	auto[0]	auto[1]	auto[0]	26	1			T114	1		T270	2		T266	5
all_values[4]	auto[0]	auto[1]	auto[1]	61	1			T16	2		T105	2		T178	2
all_values[4]	auto[1]	auto[0]	auto[1]	79	1			T16	3		T105	2		T178	2
all_values[4]	auto[1]	auto[1]	auto[1]	63	1			T16	1		T105	3		T226	2
all_values[5]	auto[0]	auto[0]	auto[0]	29	1			T178	1		T265	1		T271	4
all_values[5]	auto[0]	auto[0]	auto[1]	76	1			T16	1		T105	3		T178	2
all_values[5]	auto[0]	auto[1]	auto[0]	14	1			T115	2		T268	1		T270	1
all_values[5]	auto[0]	auto[1]	auto[1]	82	1			T16	3		T105	3		T178	2
all_values[5]	auto[1]	auto[0]	auto[1]	82	1			T16	3		T105	3		T226	2
all_values[5]	auto[1]	auto[1]	auto[1]	69	1			T16	1		T105	2		T178	2
all_values[6]	auto[0]	auto[0]	auto[0]	31	1			T16	1		T178	2		T114	1
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T16	3		T105	2		T114	5
all_values[6]	auto[0]	auto[1]	auto[0]	18	1			T178	1		T115	4		T268	1
all_values[6]	auto[0]	auto[1]	auto[1]	90	1			T16	1		T105	5		T178	2
all_values[6]	auto[1]	auto[0]	auto[1]	76	1			T16	2		T105	3		T178	1
all_values[6]	auto[1]	auto[1]	auto[1]	59	1			T16	1		T105	1		T178	1
all_values[7]	auto[0]	auto[0]	auto[0]	44	1			T105	1		T178	1		T226	1
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T105	4		T178	3		T226	1
all_values[7]	auto[0]	auto[1]	auto[0]	23	1			T226	1		T267	2		T115	1
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T16	4		T105	1		T226	1
all_values[7]	auto[1]	auto[0]	auto[1]	68	1			T16	1		T105	3		T178	1
all_values[7]	auto[1]	auto[1]	auto[1]	69	1			T16	3		T105	2		T178	2
all_values[8]	auto[0]	auto[0]	auto[0]	46	1			T105	1		T114	1		T272	1
all_values[8]	auto[0]	auto[0]	auto[1]	65	1			T16	2		T105	3		T226	2
all_values[8]	auto[0]	auto[1]	auto[0]	21	1			T226	1		T267	1		T115	1
all_values[8]	auto[0]	auto[1]	auto[1]	72	1			T16	2		T105	4		T178	4
all_values[8]	auto[1]	auto[0]	auto[1]	69	1			T16	2		T105	1		T178	1
all_values[8]	auto[1]	auto[1]	auto[1]	79	1			T16	2		T105	2		T178	2
all_values[9]	auto[0]	auto[0]	auto[0]	26	1			T105	1		T114	2		T265	2
all_values[9]	auto[0]	auto[0]	auto[1]	94	1			T16	4		T105	3		T178	3
all_values[9]	auto[0]	auto[1]	auto[0]	11	1			T114	1		T268	1		T270	1
all_values[9]	auto[0]	auto[1]	auto[1]	76	1			T16	1		T105	4		T226	2
all_values[9]	auto[1]	auto[0]	auto[1]	90	1			T16	2		T105	3		T178	3
all_values[9]	auto[1]	auto[1]	auto[1]	55	1			T16	1		T178	1		T226	1
all_values[10]	auto[0]	auto[0]	auto[0]	32	1			T16	1		T105	1		T178	3
all_values[10]	auto[0]	auto[0]	auto[1]	66	1			T16	1		T105	4		T226	3
all_values[10]	auto[0]	auto[1]	auto[0]	15	1			T226	1		T268	1		T273	1
all_values[10]	auto[0]	auto[1]	auto[1]	88	1			T16	5		T105	1		T178	1
all_values[10]	auto[1]	auto[0]	auto[1]	75	1			T16	1		T105	3		T178	2
all_values[10]	auto[1]	auto[1]	auto[1]	76	1			T105	2		T178	1		T114	3
all_values[11]	auto[0]	auto[0]	auto[0]	44	1			T16	2		T105	2		T178	2
all_values[11]	auto[0]	auto[0]	auto[1]	71	1			T16	2		T105	3		T226	2
all_values[11]	auto[0]	auto[1]	auto[0]	25	1			T267	1		T271	2		T266	1
all_values[11]	auto[0]	auto[1]	auto[1]	82	1			T16	1		T105	2		T178	2
all_values[11]	auto[1]	auto[0]	auto[1]	64	1			T16	3		T105	2		T178	2
all_values[11]	auto[1]	auto[1]	auto[1]	66	1			T105	2		T178	1		T226	4
all_values[12]	auto[0]	auto[0]	auto[0]	36	1			T16	2		T178	1		T115	1
all_values[12]	auto[0]	auto[0]	auto[1]	66	1			T16	1		T105	4		T178	2
all_values[12]	auto[0]	auto[1]	auto[0]	25	1			T16	2		T265	4		T267	2
all_values[12]	auto[0]	auto[1]	auto[1]	75	1			T16	2		T105	1		T226	3
all_values[12]	auto[1]	auto[0]	auto[1]	86	1			T16	1		T105	4		T178	3
all_values[12]	auto[1]	auto[1]	auto[1]	64	1			T105	2		T178	1		T226	3
all_values[13]	auto[0]	auto[0]	auto[0]	37	1			T16	3		T105	2		T178	1
all_values[13]	auto[0]	auto[0]	auto[1]	77	1			T105	2		T178	2		T226	2
all_values[13]	auto[0]	auto[1]	auto[0]	23	1			T16	3		T265	4		T267	1
all_values[13]	auto[0]	auto[1]	auto[1]	67	1			T16	1		T105	2		T226	2
all_values[13]	auto[1]	auto[0]	auto[1]	94	1			T16	1		T105	2		T178	3
all_values[13]	auto[1]	auto[1]	auto[1]	54	1			T105	3		T178	1		T226	2
all_values[14]	auto[0]	auto[0]	auto[0]	29	1			T178	1		T114	1		T267	2
all_values[14]	auto[0]	auto[0]	auto[1]	83	1			T16	1		T105	4		T178	1
all_values[14]	auto[0]	auto[1]	auto[0]	12	1			T226	1		T266	1		T274	1
all_values[14]	auto[0]	auto[1]	auto[1]	80	1			T16	3		T105	2		T178	3
all_values[14]	auto[1]	auto[0]	auto[1]	86	1			T16	4		T105	4		T114	3
all_values[14]	auto[1]	auto[1]	auto[1]	62	1			T105	1		T178	2		T226	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal