Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	666798	1			T1	2		T2	3		T3	4
all_values[1]	666798	1			T1	2		T2	3		T3	4
all_values[2]	666798	1			T1	2		T2	3		T3	4
all_values[3]	666798	1			T1	2		T2	3		T3	4
all_values[4]	666798	1			T1	2		T2	3		T3	4
all_values[5]	666798	1			T1	2		T2	3		T3	4
all_values[6]	666798	1			T1	2		T2	3		T3	4
all_values[7]	666798	1			T1	2		T2	3		T3	4
all_values[8]	666798	1			T1	2		T2	3		T3	4
all_values[9]	666798	1			T1	2		T2	3		T3	4
all_values[10]	666798	1			T1	2		T2	3		T3	4
all_values[11]	666798	1			T1	2		T2	3		T3	4
all_values[12]	666798	1			T1	2		T2	3		T3	4
all_values[13]	666798	1			T1	2		T2	3		T3	4
all_values[14]	666798	1			T1	2		T2	3		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8233624

1

T1

30

T2

39

T3

51

auto[1]

1768346

1

T2

6

T3

9

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9636104

1

T1

30

T2

45

T3

60

auto[1]

365866

1

T175

254697

T107

74

T34

3235

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98678	1			T1	2		T2	1		T5	2
all_values[0]	auto[0]	auto[1]	1638	1			T175	64		T107	3		T34	22
all_values[0]	auto[1]	auto[0]	543710	1			T2	2		T3	4		T4	2
all_values[0]	auto[1]	auto[1]	22772	1			T175	16940		T107	1		T34	226
all_values[1]	auto[0]	auto[0]	641405	1			T1	2		T2	3		T3	4
all_values[1]	auto[0]	auto[1]	24914	1			T175	16950		T107	3		T34	245
all_values[1]	auto[1]	auto[0]	283	1			T277	48		T35	6		T278	7
all_values[1]	auto[1]	auto[1]	196	1			T175	54		T107	1		T34	3
all_values[2]	auto[0]	auto[0]	641864	1			T1	2		T2	3		T3	4
all_values[2]	auto[0]	auto[1]	24606	1			T175	16637		T34	246		T111	707
all_values[2]	auto[1]	auto[0]	186	1			T6	1		T53	1		T279	1
all_values[2]	auto[1]	auto[1]	142	1			T175	5		T34	3		T111	2
all_values[3]	auto[0]	auto[0]	641675	1			T1	2		T2	3		T3	4
all_values[3]	auto[0]	auto[1]	24942	1			T175	16997		T107	5		T34	242
all_values[3]	auto[1]	auto[1]	181	1			T175	6		T107	1		T34	5
all_values[4]	auto[0]	auto[0]	643094	1			T1	2		T2	3		T3	4
all_values[4]	auto[0]	auto[1]	23538	1			T175	16994		T107	5		T34	245
all_values[4]	auto[1]	auto[0]	20	1			T26	2		T259	1		T90	1
all_values[4]	auto[1]	auto[1]	146	1			T175	8		T107	1		T34	3
all_values[5]	auto[0]	auto[0]	644089	1			T1	2		T2	3		T3	4
all_values[5]	auto[0]	auto[1]	22558	1			T175	16996		T107	2		T34	4
all_values[5]	auto[1]	auto[1]	151	1			T175	9		T107	3		T34	2
all_values[6]	auto[0]	auto[0]	643136	1			T1	2		T2	3		T3	4
all_values[6]	auto[0]	auto[1]	23506	1			T175	16997		T107	2		T34	243
all_values[6]	auto[1]	auto[1]	156	1			T175	7		T107	3		T34	6
all_values[7]	auto[0]	auto[0]	615524	1			T1	2		T2	2		T3	4
all_values[7]	auto[0]	auto[1]	22213	1			T175	16803		T107	5		T34	213
all_values[7]	auto[1]	auto[0]	28285	1			T2	1		T7	133		T10	85
all_values[7]	auto[1]	auto[1]	776	1			T175	200		T107	1		T34	34
all_values[8]	auto[0]	auto[0]	643136	1			T1	2		T2	3		T3	4
all_values[8]	auto[0]	auto[1]	23491	1			T175	16995		T107	2		T34	243
all_values[8]	auto[1]	auto[1]	171	1			T175	10		T107	4		T34	6
all_values[9]	auto[0]	auto[0]	155923	1			T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	4575	1			T175	588		T107	4		T34	231
all_values[9]	auto[1]	auto[0]	485753	1			T2	1		T3	1		T6	1
all_values[9]	auto[1]	auto[1]	20547	1			T175	16415		T107	2		T34	16
all_values[10]	auto[0]	auto[0]	641680	1			T1	2		T2	3		T3	4
all_values[10]	auto[0]	auto[1]	24961	1			T175	17000		T107	4		T34	246
all_values[10]	auto[1]	auto[1]	157	1			T175	5		T107	1		T34	2
all_values[11]	auto[0]	auto[0]	2366	1			T1	2		T2	1		T5	2
all_values[11]	auto[0]	auto[1]	281	1			T175	19		T107	4		T34	3
all_values[11]	auto[1]	auto[0]	639544	1			T2	2		T3	4		T4	2
all_values[11]	auto[1]	auto[1]	24607	1			T175	16985		T107	1		T34	1
all_values[12]	auto[0]	auto[0]	641645	1			T1	2		T2	3		T3	4
all_values[12]	auto[0]	auto[1]	24949	1			T175	16995		T107	3		T34	244
all_values[12]	auto[1]	auto[0]	60	1			T53	1		T279	1		T54	1
all_values[12]	auto[1]	auto[1]	144	1			T175	10		T107	3		T34	4
all_values[13]	auto[0]	auto[0]	641676	1			T1	2		T2	3		T3	4
all_values[13]	auto[0]	auto[1]	24946	1			T175	16991		T107	4		T34	245
all_values[13]	auto[1]	auto[1]	176	1			T175	12		T107	1		T34	3
all_values[14]	auto[0]	auto[0]	642372	1			T1	2		T2	3		T3	4
all_values[14]	auto[0]	auto[1]	24243	1			T175	16993		T107	2		T34	244
all_values[14]	auto[1]	auto[1]	183	1			T175	12		T107	3		T34	5