---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.i2c_core.u_fifos.AcqWriteStableBeforeHandshake_A	0	0	361237443	0	0	0
tb.dut.i2c_core.u_fifos.FmtWriteStableBeforeHandshake_A	0	0	363684497	0	0	0
tb.dut.i2c_core.u_fifos.TxWriteStableBeforeHandshake_A	0	0	363684497	0	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.LockArbDecision_A	0	0	363684497	0	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.NoReadyValidNoGrant_A	0	0	363684497	0	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReqStaysHighUntilGranted0_M	0	0	363684497	0	0	0
tb.dut.i2c_csr_assert.TlulOOBAddrErr_A	0	0	364337875	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnownO_A	0	0	363684497	363512641	0	0
tb.dut.CioSclEnKnownO_A	0	0	363684497	363512641	0	0
tb.dut.CioSclKnownO_A	0	0	363684497	363512641	0	0
tb.dut.CioSdaEnKnownO_A	0	0	363684497	363512641	0	0
tb.dut.CioSdaKnownO_A	0	0	363684497	363512641	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	363684497	90	0	0
tb.dut.IntrAcqStretchKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrAcqWtmkKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrCommandCompleteKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrControllerHaltKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrFmtWtmkKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrHostTimeoutKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrRxOflwKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrRxWtmkKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrSclInterfKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrSdaInterfKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrSdaUnstableKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrStretchTimeoutKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrTxStretchKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrTxWtmkKnownO_A	0	0	363684497	363512641	0	0
tb.dut.IntrUnexpStopKnownO_A	0	0	363684497	363512641	0	0
tb.dut.TlAReadyKnownO_A	0	0	363684497	363512641	0	0
tb.dut.TlDValidKnownO_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.AcqFifoDepthValid_A	0	0	1690	1690	0	0
tb.dut.i2c_core.FifoDepthValid_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_acq_overflow.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_acq_threshold.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_cmd_complete.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_controller_halt.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_fmt_threshold.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_host_timeout.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_rx_overflow.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_rx_threshold.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_scl_interference.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_sda_interference.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_sda_unstable.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_stretch_timeout.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_tx_stretch.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_tx_threshold.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.intr_hw_unexp_stop.IntrTKind_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.RamDepthSuffices_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.RamWidthSuffices_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.MinimalSramAw_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.MinimalSramFifoDepth_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.NoErr_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.NoSramReadWhenEmpty_A	0	0	363684497	169379961	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.NoSramWriteWhenFull_A	0	0	363684497	57990	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.OupBufWreadyAfterSramRead_A	0	0	363684497	232593	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.SramRvalidAfterRead_A	0	0	363684497	232593	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.DataKnown_A	0	0	363684497	316104	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.DepthKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.RvalidKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.WreadyKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	363684497	316104	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.DataKnown_A	0	0	363684497	205575912	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.DepthKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.RvalidKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.WreadyKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	363684497	205575912	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.MinimalSramAw_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.MinimalSramFifoDepth_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.NoErr_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.NoSramReadWhenEmpty_A	0	0	363684497	300184161	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.NoSramWriteWhenFull_A	0	0	363684497	25396267	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.OupBufWreadyAfterSramRead_A	0	0	363684497	167988	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.SramRvalidAfterRead_A	0	0	363684497	167988	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.DataKnown_A	0	0	363684497	191886	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.DepthKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.RvalidKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.WreadyKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	363684497	191886	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.DataKnown_A	0	0	363684497	116877269	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.DepthKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.RvalidKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.WreadyKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	363684497	116877269	0	0
tb.dut.i2c_core.u_fifos.u_ram_1p.CannotHaveEccAndParity_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_ram_1p.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_ram_1p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	363684497	669150	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.CheckHotOne_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.CheckNGreaterZero_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.GntImpliesReady_A	0	0	363684497	1299696	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.GntImpliesValid_A	0	0	363684497	1299696	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.GrantKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.IdxKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.IndexIsCorrect_A	0	0	363684497	1299696	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReadyAndValidImplyGrant_A	0	0	363684497	1299696	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReqAndReadyImplyGrant_A	0	0	363684497	1299696	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ReqImpliesValid_A	0	0	363684497	1299696	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.RoundRobin_A	0	0	363684497	14	0	1690
tb.dut.i2c_core.u_fifos.u_ram_arbiter.ValidKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_ram_arbiter.gen_data_port_assertion.DataFlow_A	0	0	363684497	1299696	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.MinimalSramAw_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.MinimalSramFifoDepth_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.NoErr_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.NoSramReadWhenEmpty_A	0	0	363684497	341204295	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.NoSramWriteWhenFull_A	0	0	363684497	207192	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.OupBufWreadyAfterSramRead_A	0	0	363684497	112468	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.SramRvalidAfterRead_A	0	0	363684497	112468	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.DataKnown_A	0	0	363684497	190571	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.DepthKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.RvalidKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.WreadyKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	363684497	190571	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.DataKnown_A	0	0	363684497	24482529	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.DepthKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.RvalidKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.WreadyKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	363684497	24482529	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.MinimalSramAw_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.MinimalSramFifoDepth_A	0	0	1690	1690	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.NoErr_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.NoSramReadWhenEmpty_A	0	0	363684497	341403905	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.NoSramWriteWhenFull_A	0	0	363684497	337974	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.OupBufWreadyAfterSramRead_A	0	0	363684497	117497	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.SramRvalidAfterRead_A	0	0	363684497	117497	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.DataKnown_A	0	0	363684497	167782	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.DepthKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.RvalidKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.WreadyKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	363684497	167782	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.DataKnown_A	0	0	363684497	33433449	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.DepthKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.RvalidKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.WreadyKnown_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	363684497	33433449	0	0
tb.dut.i2c_core.u_i2c_controller_fsm.SclOutputGlitch_A	0	0	363684497	3333878	0	0
tb.dut.i2c_core.u_i2c_target_fsm.AcqDepthRdCheck_A	0	0	363684497	990778	0	0
tb.dut.i2c_core.u_i2c_target_fsm.AcqFifoDeepEnough_A	0	0	363684497	363512641	0	0
tb.dut.i2c_core.u_i2c_target_fsm.SclOutputGlitch_A	0	0	363684497	57176	0	0
tb.dut.i2c_csr_assert.ctrl_rd_A	0	0	364337875	2407	0	0
tb.dut.i2c_csr_assert.host_fifo_config_rd_A	0	0	364337875	3234	0	0
tb.dut.i2c_csr_assert.host_nack_handler_timeout_rd_A	0	0	364337875	1165	0	0
tb.dut.i2c_csr_assert.host_timeout_ctrl_rd_A	0	0	364337875	808	0	0
tb.dut.i2c_csr_assert.intr_enable_rd_A	0	0	364337875	4240	0	0
tb.dut.i2c_csr_assert.ovrd_rd_A	0	0	364337875	2061	0	0
tb.dut.i2c_csr_assert.target_fifo_config_rd_A	0	0	364337875	1224	0	0
tb.dut.i2c_csr_assert.target_id_rd_A	0	0	364337875	1649	0	0
tb.dut.i2c_csr_assert.target_timeout_ctrl_rd_A	0	0	364337875	1128	0	0
tb.dut.i2c_csr_assert.timeout_ctrl_rd_A	0	0	364337875	1458	0	0
tb.dut.i2c_csr_assert.timing0_rd_A	0	0	364337875	1196	0	0
tb.dut.i2c_csr_assert.timing1_rd_A	0	0	364337875	1080	0	0
tb.dut.i2c_csr_assert.timing2_rd_A	0	0	364337875	1152	0	0
tb.dut.i2c_csr_assert.timing3_rd_A	0	0	364337875	1054	0	0
tb.dut.i2c_csr_assert.timing4_rd_A	0	0	364337875	1145	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	364337875	38632562	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	364337875	364130491	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	364337875	364130491	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	364337875	46780608	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	364337875	364130491	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	364337875	364130491	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1855	1855	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	364339010	1367117	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	364337875	35686	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	364339010	37677510	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	364339010	44947038	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	364337875	33423	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	364339010	38632629	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	364339010	46780694	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	364339010	38632629	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	364339010	46780694	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	364339010	46780694	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	364339010	46780694	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	364337875	31414	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	364337875	36477	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1855	1855	0	0
tb.dut.u_reg.en2addrHit	0	0	364337875	35431628	0	0
tb.dut.u_reg.reAfterRv	0	0	364337875	35431505	0	0
tb.dut.u_reg.rePulse	0	0	364337875	34636527	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1855	1855	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1855	1855	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1855	1855	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1855	1855	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1855	1855	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1855	1855	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1855	1855	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1855	1855	0	0
tb.dut.u_reg.wePulse	0	0	364337875	794978	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.i2c_core.u_fifos.u_ram_arbiter.RoundRobin_A	0	0	363684497	14	0	1690

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	364339010	141552	141552	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	364339010	122	122	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	364339010	130	130	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	364339010	92	92	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	364339010	21	21	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	364339010	67	67	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	364339010	75	75	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	364339010	3633	3633	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	364339010	2015590	2015590	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	364339010	19240382	19240382	1834

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	364339010	141552	141552	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	364339010	122	122	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	364339010	130	130	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	364339010	92	92	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	364339010	21	21	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	364339010	67	67	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	364339010	75	75	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	364339010	3633	3633	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	364339010	2015590	2015590	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	364339010	19240382	19240382	1834