Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	666798	1			T1	2		T2	3		T3	4
all_pins[1]	666798	1			T1	2		T2	3		T3	4
all_pins[2]	666798	1			T1	2		T2	3		T3	4
all_pins[3]	666798	1			T1	2		T2	3		T3	4
all_pins[4]	666798	1			T1	2		T2	3		T3	4
all_pins[5]	666798	1			T1	2		T2	3		T3	4
all_pins[6]	666798	1			T1	2		T2	3		T3	4
all_pins[7]	666798	1			T1	2		T2	3		T3	4
all_pins[8]	666798	1			T1	2		T2	3		T3	4
all_pins[9]	666798	1			T1	2		T2	3		T3	4
all_pins[10]	666798	1			T1	2		T2	3		T3	4
all_pins[11]	666798	1			T1	2		T2	3		T3	4
all_pins[12]	666798	1			T1	2		T2	3		T3	4
all_pins[13]	666798	1			T1	2		T2	3		T3	4
all_pins[14]	666798	1			T1	2		T2	3		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8239578	1			T1	30		T2	39		T3	51
values[0x1]	1762392	1			T2	6		T3	9		T4	4
transitions[0x0=>0x1]	1761678	1			T2	6		T3	9		T4	4
transitions[0x1=>0x0]	1760363	1			T2	5		T3	8		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	103781	1			T1	2		T2	1		T5	2
all_pins[0]	values[0x1]	563017	1			T2	2		T3	4		T4	2
all_pins[0]	transitions[0x0=>0x1]	562604	1			T2	2		T3	4		T4	2
all_pins[0]	transitions[0x1=>0x0]	57	1			T175	1		T107	1		T34	1
all_pins[1]	values[0x0]	666328	1			T1	2		T2	3		T3	4
all_pins[1]	values[0x1]	470	1			T277	64		T35	8		T278	7
all_pins[1]	transitions[0x0=>0x1]	457	1			T277	64		T35	8		T278	7
all_pins[1]	transitions[0x1=>0x0]	112	1			T6	1		T279	1		T282	1
all_pins[2]	values[0x0]	666673	1			T1	2		T2	3		T3	4
all_pins[2]	values[0x1]	125	1			T6	1		T279	1		T282	1
all_pins[2]	transitions[0x0=>0x1]	108	1			T6	1		T279	1		T282	1
all_pins[2]	transitions[0x1=>0x0]	71	1			T175	1		T34	2		T111	1
all_pins[3]	values[0x0]	666710	1			T1	2		T2	3		T3	4
all_pins[3]	values[0x1]	88	1			T175	2		T34	3		T111	1
all_pins[3]	transitions[0x0=>0x1]	75	1			T175	2		T34	3		T111	1
all_pins[3]	transitions[0x1=>0x0]	82	1			T26	3		T259	1		T90	1
all_pins[4]	values[0x0]	666703	1			T1	2		T2	3		T3	4
all_pins[4]	values[0x1]	95	1			T26	3		T259	1		T90	1
all_pins[4]	transitions[0x0=>0x1]	78	1			T26	3		T259	1		T90	1
all_pins[4]	transitions[0x1=>0x0]	60	1			T175	1		T107	3		T34	2
all_pins[5]	values[0x0]	666721	1			T1	2		T2	3		T3	4
all_pins[5]	values[0x1]	77	1			T175	3		T107	3		T34	2
all_pins[5]	transitions[0x0=>0x1]	53	1			T175	3		T34	2		T111	1
all_pins[5]	transitions[0x1=>0x0]	55	1			T175	2		T34	4		T111	2
all_pins[6]	values[0x0]	666719	1			T1	2		T2	3		T3	4
all_pins[6]	values[0x1]	79	1			T175	2		T107	3		T34	4
all_pins[6]	transitions[0x0=>0x1]	67	1			T175	2		T107	3		T34	4
all_pins[6]	transitions[0x1=>0x0]	31462	1			T2	1		T7	144		T10	93
all_pins[7]	values[0x0]	635324	1			T1	2		T2	2		T3	4
all_pins[7]	values[0x1]	31474	1			T2	1		T7	144		T10	93
all_pins[7]	transitions[0x0=>0x1]	31451	1			T2	1		T7	144		T10	93
all_pins[7]	transitions[0x1=>0x0]	61	1			T175	4		T34	5		T111	3
all_pins[8]	values[0x0]	666714	1			T1	2		T2	3		T3	4
all_pins[8]	values[0x1]	84	1			T175	4		T34	6		T111	3
all_pins[8]	transitions[0x0=>0x1]	59	1			T175	4		T34	2		T111	2
all_pins[8]	transitions[0x1=>0x0]	506216	1			T2	1		T3	1		T6	1
all_pins[9]	values[0x0]	160557	1			T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	506241	1			T2	1		T3	1		T6	1
all_pins[9]	transitions[0x0=>0x1]	506208	1			T2	1		T3	1		T6	1
all_pins[9]	transitions[0x1=>0x0]	54	1			T175	1		T34	1		T111	2
all_pins[10]	values[0x0]	666711	1			T1	2		T2	3		T3	4
all_pins[10]	values[0x1]	87	1			T175	2		T34	1		T111	3
all_pins[10]	transitions[0x0=>0x1]	63	1			T175	1		T34	1		T111	2
all_pins[10]	transitions[0x1=>0x0]	660229	1			T2	2		T3	4		T4	2
all_pins[11]	values[0x0]	6545	1			T1	2		T2	1		T5	2
all_pins[11]	values[0x1]	660253	1			T2	2		T3	4		T4	2
all_pins[11]	transitions[0x0=>0x1]	660217	1			T2	2		T3	4		T4	2
all_pins[11]	transitions[0x1=>0x0]	93	1			T53	1		T54	1		T55	1
all_pins[12]	values[0x0]	666669	1			T1	2		T2	3		T3	4
all_pins[12]	values[0x1]	129	1			T53	1		T279	1		T54	1
all_pins[12]	transitions[0x0=>0x1]	114	1			T53	1		T279	1		T54	1
all_pins[12]	transitions[0x1=>0x0]	70	1			T175	3		T107	1		T34	1
all_pins[13]	values[0x0]	666713	1			T1	2		T2	3		T3	4
all_pins[13]	values[0x1]	85	1			T175	6		T107	1		T34	1
all_pins[13]	transitions[0x0=>0x1]	67	1			T175	5		T107	1		T34	1
all_pins[13]	transitions[0x1=>0x0]	70	1			T175	7		T107	2		T34	2
all_pins[14]	values[0x0]	666710	1			T1	2		T2	3		T3	4
all_pins[14]	values[0x1]	88	1			T175	8		T107	2		T34	2
all_pins[14]	transitions[0x0=>0x1]	57	1			T175	3		T107	2		T34	1
all_pins[14]	transitions[0x1=>0x0]	561671	1			T2	1		T3	3		T4	1