Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	370	1			T175	18		T107	4		T34	8
all_values[1]	370	1			T175	18		T107	4		T34	8
all_values[2]	370	1			T175	18		T107	4		T34	8
all_values[3]	370	1			T175	18		T107	4		T34	8
all_values[4]	370	1			T175	18		T107	4		T34	8
all_values[5]	370	1			T175	18		T107	4		T34	8
all_values[6]	370	1			T175	18		T107	4		T34	8
all_values[7]	370	1			T175	18		T107	4		T34	8
all_values[8]	370	1			T175	18		T107	4		T34	8
all_values[9]	370	1			T175	18		T107	4		T34	8
all_values[10]	370	1			T175	18		T107	4		T34	8
all_values[11]	370	1			T175	18		T107	4		T34	8
all_values[12]	370	1			T175	18		T107	4		T34	8
all_values[13]	370	1			T175	18		T107	4		T34	8
all_values[14]	370	1			T175	18		T107	4		T34	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2929

1

T175

150

T107

30

T34

68

auto[1]

2621

1

T175

120

T107

30

T34

52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

943

1

T175

23

T107

14

T34

22

auto[1]

4607

1

T175

247

T107

46

T34

98

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3303

1

T175

157

T107

41

T34

78

auto[1]

2247

1

T175

113

T107

19

T34

42

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	36	1			T175	1		T107	1		T34	1
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T175	7		T107	1		T34	2
all_values[0]	auto[0]	auto[1]	auto[0]	32	1			T107	1		T111	2		T283	1
all_values[0]	auto[0]	auto[1]	auto[1]	71	1			T175	4		T34	3		T284	2
all_values[0]	auto[1]	auto[0]	auto[1]	90	1			T175	2		T34	2		T111	3
all_values[0]	auto[1]	auto[1]	auto[1]	56	1			T175	4		T107	1		T111	2
all_values[1]	auto[0]	auto[0]	auto[0]	46	1			T175	1		T107	1		T34	1
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T175	7		T34	4		T111	3
all_values[1]	auto[0]	auto[1]	auto[0]	17	1			T107	1		T258	1		T116	1
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T175	5		T107	1		T111	3
all_values[1]	auto[1]	auto[0]	auto[1]	75	1			T175	3		T34	1		T284	2
all_values[1]	auto[1]	auto[1]	auto[1]	70	1			T175	2		T107	1		T34	2
all_values[2]	auto[0]	auto[0]	auto[0]	39	1			T175	5		T107	2		T285	1
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T175	1		T34	1		T111	3
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T175	3		T107	2		T254	1
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T175	4		T34	4		T111	6
all_values[2]	auto[1]	auto[0]	auto[1]	77	1			T175	2		T34	2		T284	2
all_values[2]	auto[1]	auto[1]	auto[1]	65	1			T175	3		T34	1		T111	2
all_values[3]	auto[0]	auto[0]	auto[0]	35	1			T175	1		T34	1		T111	1
all_values[3]	auto[0]	auto[0]	auto[1]	95	1			T175	4		T34	3		T111	2
all_values[3]	auto[0]	auto[1]	auto[0]	18	1			T175	1		T34	1		T111	1
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T175	5		T107	3		T34	1
all_values[3]	auto[1]	auto[0]	auto[1]	83	1			T175	4		T107	1		T111	2
all_values[3]	auto[1]	auto[1]	auto[1]	73	1			T175	3		T34	2		T111	3
all_values[4]	auto[0]	auto[0]	auto[0]	35	1			T175	3		T34	1		T284	2
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T175	5		T107	3		T34	2
all_values[4]	auto[0]	auto[1]	auto[0]	20	1			T111	1		T116	1		T254	4
all_values[4]	auto[0]	auto[1]	auto[1]	100	1			T175	2		T34	2		T111	6
all_values[4]	auto[1]	auto[0]	auto[1]	81	1			T175	4		T107	1		T34	2
all_values[4]	auto[1]	auto[1]	auto[1]	65	1			T175	4		T34	1		T111	4
all_values[5]	auto[0]	auto[0]	auto[0]	56	1			T107	1		T34	2		T111	1
all_values[5]	auto[0]	auto[0]	auto[1]	69	1			T175	8		T284	2		T258	3
all_values[5]	auto[0]	auto[1]	auto[0]	36	1			T34	2		T111	3		T258	1
all_values[5]	auto[0]	auto[1]	auto[1]	68	1			T175	1		T107	2		T34	2
all_values[5]	auto[1]	auto[0]	auto[1]	75	1			T175	6		T34	1		T284	4
all_values[5]	auto[1]	auto[1]	auto[1]	66	1			T175	3		T107	1		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	44	1			T175	1		T107	1		T284	1
all_values[6]	auto[0]	auto[0]	auto[1]	93	1			T175	9		T34	2		T111	2
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T111	2		T116	1		T254	3
all_values[6]	auto[0]	auto[1]	auto[1]	64	1			T175	2		T107	2		T34	2
all_values[6]	auto[1]	auto[0]	auto[1]	67	1			T175	3		T34	1		T284	2
all_values[6]	auto[1]	auto[1]	auto[1]	73	1			T175	3		T107	1		T34	3
all_values[7]	auto[0]	auto[0]	auto[0]	28	1			T175	2		T34	2		T284	1
all_values[7]	auto[0]	auto[0]	auto[1]	94	1			T175	3		T34	2		T111	3
all_values[7]	auto[0]	auto[1]	auto[0]	27	1			T111	4		T258	1		T116	1
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T175	6		T107	3		T34	1
all_values[7]	auto[1]	auto[0]	auto[1]	80	1			T175	5		T107	1		T34	2
all_values[7]	auto[1]	auto[1]	auto[1]	68	1			T175	2		T34	1		T111	1
all_values[8]	auto[0]	auto[0]	auto[0]	42	1			T283	1		T254	2		T117	1
all_values[8]	auto[0]	auto[0]	auto[1]	63	1			T175	5		T107	1		T111	2
all_values[8]	auto[0]	auto[1]	auto[0]	32	1			T111	1		T116	1		T254	2
all_values[8]	auto[0]	auto[1]	auto[1]	81	1			T175	3		T34	4		T111	1
all_values[8]	auto[1]	auto[0]	auto[1]	87	1			T175	5		T107	3		T34	2
all_values[8]	auto[1]	auto[1]	auto[1]	65	1			T175	5		T34	2		T111	5
all_values[9]	auto[0]	auto[0]	auto[0]	36	1			T175	1		T34	2		T258	1
all_values[9]	auto[0]	auto[0]	auto[1]	75	1			T175	5		T107	1		T111	3
all_values[9]	auto[0]	auto[1]	auto[0]	14	1			T175	1		T117	1		T286	6
all_values[9]	auto[0]	auto[1]	auto[1]	97	1			T175	4		T107	2		T34	2
all_values[9]	auto[1]	auto[0]	auto[1]	66	1			T175	1		T107	1		T34	1
all_values[9]	auto[1]	auto[1]	auto[1]	82	1			T175	6		T34	3		T111	3
all_values[10]	auto[0]	auto[0]	auto[0]	30	1			T107	1		T34	1		T284	1
all_values[10]	auto[0]	auto[0]	auto[1]	72	1			T175	8		T107	1		T34	4
all_values[10]	auto[0]	auto[1]	auto[0]	26	1			T287	3		T286	1		T288	2
all_values[10]	auto[0]	auto[1]	auto[1]	85	1			T175	5		T107	1		T34	1
all_values[10]	auto[1]	auto[0]	auto[1]	85	1			T175	5		T107	1		T34	1
all_values[10]	auto[1]	auto[1]	auto[1]	72	1			T34	1		T111	2		T284	1
all_values[11]	auto[0]	auto[0]	auto[0]	30	1			T175	1		T107	1		T34	3
all_values[11]	auto[0]	auto[0]	auto[1]	60	1			T175	3		T34	1		T111	2
all_values[11]	auto[0]	auto[1]	auto[0]	19	1			T34	3		T283	1		T118	1
all_values[11]	auto[0]	auto[1]	auto[1]	100	1			T175	7		T107	2		T111	4
all_values[11]	auto[1]	auto[0]	auto[1]	79	1			T175	4		T34	1		T111	3
all_values[11]	auto[1]	auto[1]	auto[1]	82	1			T175	3		T107	1		T111	2
all_values[12]	auto[0]	auto[0]	auto[0]	41	1			T34	1		T284	1		T258	1
all_values[12]	auto[0]	auto[0]	auto[1]	69	1			T175	4		T34	1		T111	1
all_values[12]	auto[0]	auto[1]	auto[0]	37	1			T111	2		T283	1		T118	3
all_values[12]	auto[0]	auto[1]	auto[1]	79	1			T175	4		T107	1		T34	2
all_values[12]	auto[1]	auto[0]	auto[1]	79	1			T175	3		T107	3		T34	3
all_values[12]	auto[1]	auto[1]	auto[1]	65	1			T175	7		T34	1		T111	2
all_values[13]	auto[0]	auto[0]	auto[0]	36	1			T175	2		T107	1		T34	1
all_values[13]	auto[0]	auto[0]	auto[1]	83	1			T175	3		T34	4		T111	3
all_values[13]	auto[0]	auto[1]	auto[0]	18	1			T111	1		T258	1		T286	1
all_values[13]	auto[0]	auto[1]	auto[1]	73	1			T175	2		T107	2		T34	1
all_values[13]	auto[1]	auto[0]	auto[1]	76	1			T175	4		T34	2		T284	2
all_values[13]	auto[1]	auto[1]	auto[1]	84	1			T175	7		T107	1		T111	4
all_values[14]	auto[0]	auto[0]	auto[0]	32	1			T107	1		T116	3		T289	1
all_values[14]	auto[0]	auto[0]	auto[1]	85	1			T175	4		T34	3		T111	5
all_values[14]	auto[0]	auto[1]	auto[0]	21	1			T111	4		T258	1		T116	2
all_values[14]	auto[0]	auto[1]	auto[1]	71	1			T175	4		T107	1		T34	2
all_values[14]	auto[1]	auto[0]	auto[1]	91	1			T175	5		T107	2		T34	2
all_values[14]	auto[1]	auto[1]	auto[1]	70	1			T175	5		T34	1		T111	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal