Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30450544	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8244924

1

T1

33

T2

4098

T3

42

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37842619	1			T1	1848		T2	29897		T3	25
values[0x0]	425308	1			T1	22		T2	271		T3	42
values[0x1]	427541	1			T1	31		T2	256		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21342118	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17353350

1

T1

478

T2

12256

T3

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	146078	1			T1	13		T2	222		T3	3
valid_sources[0x01]	171467	1			T1	5		T2	105		T5	662
valid_sources[0x02]	147961	1			T2	54		T5	833		T6	9
valid_sources[0x03]	144769	1			T2	127		T5	751		T6	7
valid_sources[0x04]	157281	1			T1	7		T2	121		T3	1
valid_sources[0x05]	140160	1			T1	7		T2	231		T3	1
valid_sources[0x06]	209668	1			T1	6		T2	15		T5	561
valid_sources[0x07]	160670	1			T1	11		T2	131		T5	560
valid_sources[0x08]	150793	1			T1	9		T2	37		T5	607
valid_sources[0x09]	135944	1			T2	124		T3	4		T5	499
valid_sources[0x0a]	145103	1			T1	3		T2	78		T5	800
valid_sources[0x0b]	144887	1			T2	19		T5	764		T6	2
valid_sources[0x0c]	147363	1			T1	4		T2	162		T4	1
valid_sources[0x0d]	155081	1			T1	4		T2	137		T4	1
valid_sources[0x0e]	152321	1			T1	10		T2	211		T5	617
valid_sources[0x0f]	142542	1			T1	13		T2	53		T5	511
valid_sources[0x10]	145045	1			T1	4		T2	129		T5	644
valid_sources[0x11]	153166	1			T1	14		T2	118		T5	610
valid_sources[0x12]	146654	1			T1	7		T2	91		T5	556
valid_sources[0x13]	137625	1			T1	4		T2	177		T5	772
valid_sources[0x14]	148882	1			T1	1		T2	124		T3	1
valid_sources[0x15]	153856	1			T1	2		T2	121		T3	1
valid_sources[0x16]	148137	1			T1	1		T2	109		T5	667
valid_sources[0x17]	143716	1			T1	11		T2	68		T5	565
valid_sources[0x18]	142306	1			T1	7		T2	220		T3	1
valid_sources[0x19]	149752	1			T1	12		T2	201		T5	712
valid_sources[0x1a]	139605	1			T1	22		T2	181		T3	1
valid_sources[0x1b]	145118	1			T1	3		T2	173		T5	705
valid_sources[0x1c]	156209	1			T1	16		T2	129		T5	595
valid_sources[0x1d]	142085	1			T1	9		T2	71		T5	667
valid_sources[0x1e]	142283	1			T2	95		T5	531		T6	1
valid_sources[0x1f]	134358	1			T1	3		T2	150		T5	474
valid_sources[0x20]	148434	1			T1	7		T2	52		T4	1
valid_sources[0x21]	151235	1			T1	14		T2	112		T5	715
valid_sources[0x22]	154084	1			T1	7		T2	141		T5	567
valid_sources[0x23]	151971	1			T1	1		T2	226		T3	1
valid_sources[0x24]	157364	1			T1	3		T2	120		T5	525
valid_sources[0x25]	166447	1			T1	6		T2	131		T3	3
valid_sources[0x26]	148220	1			T1	6		T2	135		T3	4
valid_sources[0x27]	148248	1			T1	9		T2	164		T3	1
valid_sources[0x28]	149713	1			T1	1		T2	140		T5	642
valid_sources[0x29]	153851	1			T1	22		T2	67		T3	1
valid_sources[0x2a]	155383	1			T1	4		T2	32		T5	588
valid_sources[0x2b]	167257	1			T1	15		T2	44		T3	2
valid_sources[0x2c]	153939	1			T1	7		T2	164		T3	1
valid_sources[0x2d]	236357	1			T1	12		T2	14		T5	429
valid_sources[0x2e]	143020	1			T1	10		T2	107		T4	1
valid_sources[0x2f]	139953	1			T1	3		T2	23		T5	630
valid_sources[0x30]	144308	1			T1	14		T2	118		T5	585
valid_sources[0x31]	157895	1			T1	11		T2	108		T5	743
valid_sources[0x32]	140376	1			T1	26		T2	125		T3	2
valid_sources[0x33]	154122	1			T1	16		T2	101		T3	1
valid_sources[0x34]	153194	1			T1	6		T2	117		T5	533
valid_sources[0x35]	146965	1			T1	5		T2	52		T5	648
valid_sources[0x36]	156985	1			T1	14		T2	136		T5	632
valid_sources[0x37]	149751	1			T1	9		T2	135		T3	3
valid_sources[0x38]	153135	1			T1	7		T2	134		T5	617
valid_sources[0x39]	164638	1			T1	16		T2	47		T5	703
valid_sources[0x3a]	181644	1			T1	10		T2	258		T5	688
valid_sources[0x3b]	147375	1			T1	3		T2	129		T4	1
valid_sources[0x3c]	149962	1			T1	3		T2	158		T4	1
valid_sources[0x3d]	158532	1			T1	10		T2	106		T3	6
valid_sources[0x3e]	165698	1			T1	12		T2	195		T5	644
valid_sources[0x3f]	137731	1			T1	7		T2	141		T5	711
valid_sources[0x40]	162826	1			T1	7		T2	106		T3	1
valid_sources[0x41]	158416	1			T1	7		T2	79		T5	435
valid_sources[0x42]	170965	1			T1	11		T2	139		T5	597
valid_sources[0x43]	142209	1			T1	6		T2	64		T5	481
valid_sources[0x44]	150962	1			T1	25		T2	104		T5	507
valid_sources[0x45]	144262	1			T1	4		T2	214		T3	1
valid_sources[0x46]	146878	1			T1	9		T2	130		T5	889
valid_sources[0x47]	170902	1			T1	6		T2	80		T5	566
valid_sources[0x48]	156757	1			T1	4		T2	181		T5	773
valid_sources[0x49]	146072	1			T1	3		T2	153		T5	763
valid_sources[0x4a]	138762	1			T1	9		T2	257		T5	599
valid_sources[0x4b]	144794	1			T1	2		T2	90		T3	1
valid_sources[0x4c]	157662	1			T1	5		T2	169		T5	538
valid_sources[0x4d]	149467	1			T1	7		T2	121		T4	1
valid_sources[0x4e]	147758	1			T1	4		T2	58		T5	667
valid_sources[0x4f]	144412	1			T1	6		T2	51		T5	649
valid_sources[0x50]	148934	1			T2	119		T5	478		T6	6
valid_sources[0x51]	160233	1			T1	8		T2	91		T4	1
valid_sources[0x52]	140192	1			T1	28		T2	80		T5	610
valid_sources[0x53]	158906	1			T1	16		T2	127		T3	1
valid_sources[0x54]	145499	1			T1	6		T2	138		T5	642
valid_sources[0x55]	141598	1			T1	7		T2	17		T5	739
valid_sources[0x56]	144577	1			T1	1		T2	202		T3	3
valid_sources[0x57]	137902	1			T1	11		T2	100		T5	686
valid_sources[0x58]	147698	1			T1	2		T2	147		T5	719
valid_sources[0x59]	140093	1			T1	4		T2	118		T5	626
valid_sources[0x5a]	150713	1			T1	7		T2	187		T5	602
valid_sources[0x5b]	140424	1			T1	19		T2	134		T5	563
valid_sources[0x5c]	145501	1			T1	9		T2	130		T4	2
valid_sources[0x5d]	147622	1			T1	8		T2	154		T3	2
valid_sources[0x5e]	151395	1			T1	1		T2	125		T5	514
valid_sources[0x5f]	147322	1			T1	6		T2	235		T5	503
valid_sources[0x60]	145784	1			T1	12		T2	127		T3	4
valid_sources[0x61]	159976	1			T1	13		T2	131		T4	3
valid_sources[0x62]	134163	1			T2	47		T4	1		T5	556
valid_sources[0x63]	155671	1			T1	4		T2	149		T5	653
valid_sources[0x64]	156053	1			T1	13		T2	200		T5	592
valid_sources[0x65]	152191	1			T1	15		T2	159		T3	2
valid_sources[0x66]	145893	1			T1	14		T2	100		T5	829
valid_sources[0x67]	172189	1			T1	4		T2	75		T5	435
valid_sources[0x68]	138048	1			T1	25		T2	133		T5	470
valid_sources[0x69]	151638	1			T1	6		T2	122		T5	607
valid_sources[0x6a]	138334	1			T1	19		T2	108		T5	658
valid_sources[0x6b]	171220	1			T1	15		T2	37		T5	609
valid_sources[0x6c]	146739	1			T1	4		T2	96		T5	753
valid_sources[0x6d]	152755	1			T1	8		T2	90		T3	3
valid_sources[0x6e]	144325	1			T1	3		T2	162		T5	594
valid_sources[0x6f]	148832	1			T2	217		T5	656		T6	2
valid_sources[0x70]	146875	1			T2	93		T5	536		T6	2
valid_sources[0x71]	151478	1			T1	6		T2	70		T5	622
valid_sources[0x72]	158048	1			T1	4		T2	100		T5	507
valid_sources[0x73]	154743	1			T1	5		T2	144		T4	1
valid_sources[0x74]	147283	1			T1	1		T2	22		T5	680
valid_sources[0x75]	152793	1			T1	10		T2	182		T4	2
valid_sources[0x76]	139274	1			T1	3		T2	138		T5	710
valid_sources[0x77]	141806	1			T1	8		T2	63		T5	623
valid_sources[0x78]	143667	1			T1	16		T2	84		T4	1
valid_sources[0x79]	171373	1			T2	286		T5	620		T6	3
valid_sources[0x7a]	156818	1			T1	8		T2	45		T5	647
valid_sources[0x7b]	167102	1			T1	7		T2	89		T5	723
valid_sources[0x7c]	140857	1			T1	11		T2	98		T4	1
valid_sources[0x7d]	134682	1			T1	9		T2	181		T3	1
valid_sources[0x7e]	151254	1			T1	10		T2	31		T3	1
valid_sources[0x7f]	147034	1			T1	6		T2	124		T3	1
valid_sources[0x80]	157698	1			T1	2		T2	90		T5	593

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7865585

1

T1

8

T2

3743

T3

5

values[0x0]

all_enables

biggest_size

224681

1

T1

14

T2

193

T3

18

values[0x1]

all_enables

biggest_size

154658

1

T1

11

T2

162

T3

19