Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	425281334	0	0	0
ctrl_rd_A	425281334	3684	0	0
host_fifo_config_rd_A	425281334	6771	0	0
host_nack_handler_timeout_rd_A	425281334	2431	0	0
host_timeout_ctrl_rd_A	425281334	2152	0	0
intr_enable_rd_A	425281334	5680	0	0
ovrd_rd_A	425281334	3401	0	0
target_fifo_config_rd_A	425281334	2507	0	0
target_id_rd_A	425281334	3020	0	0
target_timeout_ctrl_rd_A	425281334	2354	0	0
timeout_ctrl_rd_A	425281334	2799	0	0
timing0_rd_A	425281334	2402	0	0
timing1_rd_A	425281334	2453	0	0
timing2_rd_A	425281334	2485	0	0
timing3_rd_A	425281334	2428	0	0
timing4_rd_A	425281334	2425	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	3684	0	0
T96	14014	290	0	0
T97	7590	81	0	0
T98	14342	404	0	0
T99	2849	28	0	0
T100	1342	3	0	0
T101	13652	191	0	0
T102	1554	18	0	0
T103	26690	204	0	0
T104	5575	115	0	0
T105	52527	411	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	6771	0	0
T38	486952	58	0	0
T54	47261	0	0	0
T76	0	210	0	0
T92	2632	0	0	0
T106	0	150	0	0
T107	0	194	0	0
T108	0	95	0	0
T109	0	128	0	0
T110	0	105	0	0
T111	0	129	0	0
T112	0	52	0	0
T113	0	220	0	0
T114	14985	0	0	0
T115	93798	0	0	0
T116	1215	0	0	0
T117	7678	0	0	0
T118	14876	0	0	0
T119	34433	0	0	0
T120	1380	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	2431	0	0
T96	14014	130	0	0
T97	7590	24	0	0
T98	14342	147	0	0
T99	2849	7	0	0
T100	1342	2	0	0
T101	13652	116	0	0
T103	26690	203	0	0
T104	5575	108	0	0
T105	52527	438	0	0
T121	7650	47	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	2152	0	0
T96	14014	60	0	0
T97	7590	27	0	0
T98	14342	65	0	0
T99	2849	6	0	0
T101	13652	64	0	0
T103	26690	210	0	0
T104	5575	114	0	0
T105	52527	470	0	0
T121	7650	35	0	0
T122	7009	60	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	5680	0	0
T96	0	576	0	0
T97	0	109	0	0
T98	0	740	0	0
T99	0	74	0	0
T123	221139	28	0	0
T124	0	10	0	0
T125	0	28	0	0
T126	0	18	0	0
T127	0	8	0	0
T128	0	5	0	0
T129	288261	0	0	0
T130	106514	0	0	0
T131	91381	0	0	0
T132	875214	0	0	0
T133	75243	0	0	0
T134	256655	0	0	0
T135	66291	0	0	0
T136	149669	0	0	0
T137	41109	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	3401	0	0
T21	29320	0	0	0
T27	90477	0	0	0
T31	10128	0	0	0
T69	50106	0	0	0
T74	1916	61	0	0
T93	0	32	0	0
T138	0	35	0	0
T139	0	7	0	0
T140	0	48	0	0
T141	0	52	0	0
T142	0	61	0	0
T143	0	55	0	0
T144	0	45	0	0
T145	0	36	0	0
T146	4813	0	0	0
T147	252461	0	0	0
T148	464347	0	0	0
T149	9056	0	0	0
T150	40260	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	2507	0	0
T96	14014	127	0	0
T97	7590	10	0	0
T98	14342	98	0	0
T99	2849	19	0	0
T100	1342	1	0	0
T101	13652	87	0	0
T102	1554	7	0	0
T103	26690	207	0	0
T104	5575	89	0	0
T105	52527	491	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	3020	0	0
T96	14014	174	0	0
T97	7590	90	0	0
T98	14342	242	0	0
T99	2849	25	0	0
T101	13652	169	0	0
T102	1554	27	0	0
T103	26690	253	0	0
T104	5575	107	0	0
T105	52527	461	0	0
T121	7650	104	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	2354	0	0
T96	14014	83	0	0
T97	7590	46	0	0
T98	14342	113	0	0
T99	2849	6	0	0
T100	1342	7	0	0
T101	13652	107	0	0
T102	1554	4	0	0
T103	26690	241	0	0
T104	5575	120	0	0
T105	52527	402	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	2799	0	0
T96	14014	156	0	0
T97	7590	51	0	0
T98	14342	158	0	0
T99	2849	23	0	0
T100	1342	3	0	0
T101	13652	162	0	0
T102	1554	10	0	0
T103	26690	244	0	0
T104	5575	120	0	0
T105	52527	436	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	2402	0	0
T96	14014	127	0	0
T97	7590	42	0	0
T98	14342	108	0	0
T99	2849	5	0	0
T100	1342	4	0	0
T101	13652	123	0	0
T102	1554	4	0	0
T103	26690	184	0	0
T104	5575	108	0	0
T105	52527	449	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	2453	0	0
T96	14014	89	0	0
T97	7590	32	0	0
T98	14342	113	0	0
T99	2849	15	0	0
T100	1342	3	0	0
T101	13652	125	0	0
T102	1554	7	0	0
T103	26690	191	0	0
T104	5575	110	0	0
T105	52527	473	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	2485	0	0
T96	14014	115	0	0
T97	7590	37	0	0
T98	14342	123	0	0
T99	2849	5	0	0
T100	1342	8	0	0
T101	13652	92	0	0
T103	26690	227	0	0
T104	5575	106	0	0
T105	52527	415	0	0
T121	7650	108	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	2428	0	0
T96	14014	82	0	0
T97	7590	37	0	0
T98	14342	103	0	0
T99	2849	22	0	0
T100	1342	7	0	0
T101	13652	112	0	0
T102	1554	3	0	0
T103	26690	231	0	0
T104	5575	90	0	0
T105	52527	440	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425281334	2425	0	0
T96	14014	96	0	0
T97	7590	27	0	0
T98	14342	122	0	0
T99	2849	8	0	0
T100	1342	1	0	0
T101	13652	85	0	0
T102	1554	8	0	0
T103	26690	190	0	0
T104	5575	117	0	0
T105	52527	402	0	0