Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	636898	1			T2	2		T3	144		T4	2
all_values[1]	636898	1			T2	2		T3	144		T4	2
all_values[2]	636898	1			T2	2		T3	144		T4	2
all_values[3]	636898	1			T2	2		T3	144		T4	2
all_values[4]	636898	1			T2	2		T3	144		T4	2
all_values[5]	636898	1			T2	2		T3	144		T4	2
all_values[6]	636898	1			T2	2		T3	144		T4	2
all_values[7]	636898	1			T2	2		T3	144		T4	2
all_values[8]	636898	1			T2	2		T3	144		T4	2
all_values[9]	636898	1			T2	2		T3	144		T4	2
all_values[10]	636898	1			T2	2		T3	144		T4	2
all_values[11]	636898	1			T2	2		T3	144		T4	2
all_values[12]	636898	1			T2	2		T3	144		T4	2
all_values[13]	636898	1			T2	2		T3	144		T4	2
all_values[14]	636898	1			T2	2		T3	144		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7880364

1

T2

26

T3

1950

T4

26

auto[1]

1673106

1

T2

4

T3

210

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9196699

1

T2

30

T3

2160

T4

30

auto[1]

356771

1

T21

61

T27

75

T188

78

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104940	1			T3	129		T10	1		T14	1309
all_values[0]	auto[0]	auto[1]	2990	1			T21	3		T27	3		T188	3
all_values[0]	auto[1]	auto[0]	506857	1			T2	2		T3	15		T4	2
all_values[0]	auto[1]	auto[1]	22111	1			T21	2		T27	3		T188	3
all_values[1]	auto[0]	auto[0]	611297	1			T2	2		T3	144		T4	2
all_values[1]	auto[0]	auto[1]	24929	1			T21	3		T27	3		T188	3
all_values[1]	auto[1]	auto[0]	484	1			T41	5		T105	4		T273	10
all_values[1]	auto[1]	auto[1]	188	1			T21	3		T27	1		T188	3
all_values[2]	auto[0]	auto[0]	611589	1			T2	2		T3	144		T4	2
all_values[2]	auto[0]	auto[1]	24970	1			T21	5		T27	3		T188	4
all_values[2]	auto[1]	auto[0]	184	1			T53	1		T71	1		T274	2
all_values[2]	auto[1]	auto[1]	155	1			T21	1		T27	3		T188	2
all_values[3]	auto[0]	auto[0]	611782	1			T2	2		T3	144		T4	2
all_values[3]	auto[0]	auto[1]	24933	1			T21	3		T27	5		T188	5
all_values[3]	auto[1]	auto[1]	183	1			T21	3		T27	1		T188	1
all_values[4]	auto[0]	auto[0]	611790	1			T2	2		T3	144		T4	2
all_values[4]	auto[0]	auto[1]	24924	1			T21	4		T27	3		T188	5
all_values[4]	auto[1]	auto[0]	8	1			T23	1		T259	1		T262	1
all_values[4]	auto[1]	auto[1]	176	1			T21	1		T27	3		T188	1
all_values[5]	auto[0]	auto[0]	614477	1			T2	2		T3	144		T4	2
all_values[5]	auto[0]	auto[1]	22236	1			T21	2		T188	2		T189	7
all_values[5]	auto[1]	auto[1]	185	1			T21	2		T188	3		T189	2
all_values[6]	auto[0]	auto[0]	611776	1			T2	2		T3	144		T4	2
all_values[6]	auto[0]	auto[1]	24933	1			T27	4		T188	2		T189	4
all_values[6]	auto[1]	auto[1]	189	1			T27	1		T188	4		T189	3
all_values[7]	auto[0]	auto[0]	586326	1			T2	2		T3	91		T4	2
all_values[7]	auto[0]	auto[1]	24099	1			T21	4		T27	4		T188	2
all_values[7]	auto[1]	auto[0]	25455	1			T3	53		T16	275		T15	154
all_values[7]	auto[1]	auto[1]	1018	1			T21	2		T188	3		T189	4
all_values[8]	auto[0]	auto[0]	611782	1			T2	2		T3	144		T4	2
all_values[8]	auto[0]	auto[1]	24941	1			T21	5		T27	2		T188	2
all_values[8]	auto[1]	auto[1]	175	1			T21	1		T27	3		T188	3
all_values[9]	auto[0]	auto[0]	151957	1			T2	2		T3	144		T4	2
all_values[9]	auto[0]	auto[1]	4137	1			T27	2		T188	3		T189	5
all_values[9]	auto[1]	auto[0]	459830	1			T10	1		T45	1		T14	3
all_values[9]	auto[1]	auto[1]	20974	1			T27	4		T188	2		T189	4
all_values[10]	auto[0]	auto[0]	611786	1			T2	2		T3	144		T4	2
all_values[10]	auto[0]	auto[1]	24938	1			T27	3		T188	5		T189	5
all_values[10]	auto[1]	auto[1]	174	1			T27	2		T188	1		T189	4
all_values[11]	auto[0]	auto[0]	2429	1			T3	2		T10	1		T14	3
all_values[11]	auto[0]	auto[1]	296	1			T21	4		T27	3		T188	3
all_values[11]	auto[1]	auto[0]	609348	1			T2	2		T3	142		T4	2
all_values[11]	auto[1]	auto[1]	24825	1			T21	2		T27	3		T188	3
all_values[12]	auto[0]	auto[0]	611838	1			T2	2		T3	144		T4	2
all_values[12]	auto[0]	auto[1]	24834	1			T21	4		T27	3		T189	6
all_values[12]	auto[1]	auto[0]	62	1			T53	1		T71	1		T72	1
all_values[12]	auto[1]	auto[1]	164	1			T21	1		T27	3		T189	1
all_values[13]	auto[0]	auto[0]	614488	1			T2	2		T3	144		T4	2
all_values[13]	auto[0]	auto[1]	22229	1			T27	4		T188	2		T189	6
all_values[13]	auto[1]	auto[1]	181	1			T188	4		T242	12		T275	4
all_values[14]	auto[0]	auto[0]	626214	1			T2	2		T3	144		T4	2
all_values[14]	auto[0]	auto[1]	10504	1			T21	5		T27	5		T188	4
all_values[14]	auto[1]	auto[1]	180	1			T21	1		T27	1		T189	5