Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.93 95.86 88.01 97.22 71.43 88.91 98.15


Total modules in report: 40
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
i2c_fifos 80.00 100.00 100.00 40.00
i2c_controller_fsm 82.79 89.89 75.18 64.71 84.15 100.00
i2c_target_fsm 86.20 93.80 80.00 73.58 83.64 100.00
i2c_bus_monitor 89.50 96.26 90.32 81.82 89.58
prim_arbiter_tree 90.93 100.00 82.46 100.00 81.25
  tlul_rsp_intg_gen 91.67 83.33 100.00
i2c_core 92.58 97.74 79.23 93.33 100.00
i2c_csr_assert_fpv 93.75 93.75
prim_generic_ram_1p 95.24 85.71 100.00 100.00
  i2c_fifo_sync_sram_adapter 95.59 100.00 82.35 100.00 100.00
prim_fifo_sync 95.83 100.00 83.33 100.00 100.00
  prim_subreg_arb 95.83 87.50 100.00 100.00
  prim_subreg 96.75 100.00 97.40 92.86
i2c 98.48 100.00 100.00 93.91 100.00
tlul_adapter_reg 98.91 100.00 95.65 100.00 100.00
i2c_reg_top 99.64 100.00 98.56 100.00 100.00
  prim_fifo_sync_cnt 100.00 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_onehot_check 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
  prim_intr_hw 100.00 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_ram_1p_adv 100.00 100.00 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb
prim_ram_1p